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frontend/ir_emitter: Add half-precision opcode variant of FPRSqrtStepFused

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Lioncash 2019-04-14 20:55:25 -04:00 committed by MerryMage
parent e3b2eb57b5
commit 824c551ba2
5 changed files with 57 additions and 40 deletions
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6
src/backend/x64/emit_x64_floating_point.cpp
View file

@ -946,6 +946,7 @@ template<size_t fsize>
static void EmitFPRSqrtStepFused(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) {
using FPT = mp::unsigned_integer_of_size<fsize>;
if constexpr (fsize != 16) {
if (code.DoesCpuSupport(Xbyak::util::Cpu::tFMA) && code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
@ -993,6 +994,7 @@ static void EmitFPRSqrtStepFused(BlockOfCode& code, EmitContext& ctx, IR::Inst*
ctx.reg_alloc.DefineValue(inst, result);
return;
}
}
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
ctx.reg_alloc.HostCall(inst, args[0], args[1]);
@ -1001,6 +1003,10 @@ static void EmitFPRSqrtStepFused(BlockOfCode& code, EmitContext& ctx, IR::Inst*
code.CallFunction(&FP::FPRSqrtStepFused<FPT>);
}
void EmitX64::EmitFPRSqrtStepFused16(EmitContext& ctx, IR::Inst* inst) {
EmitFPRSqrtStepFused<16>(code, ctx, inst);
}
void EmitX64::EmitFPRSqrtStepFused32(EmitContext& ctx, IR::Inst* inst) {
EmitFPRSqrtStepFused<32>(code, ctx, inst);
}

15
src/frontend/ir/ir_emitter.cpp
View file

@ -1997,11 +1997,20 @@ U16U32U64 IREmitter::FPRSqrtEstimate(const U16U32U64& a) {
}
}
U32U64 IREmitter::FPRSqrtStepFused(const U32U64& a, const U32U64& b) {
if (a.GetType() == Type::U32) {
U16U32U64 IREmitter::FPRSqrtStepFused(const U16U32U64& a, const U16U32U64& b) {
ASSERT(a.GetType() == b.GetType());
switch (a.GetType()) {
case Type::U16:
return Inst<U16>(Opcode::FPRSqrtStepFused16, a, b);
case Type::U32:
return Inst<U32>(Opcode::FPRSqrtStepFused32, a, b);
}
case Type::U64:
return Inst<U64>(Opcode::FPRSqrtStepFused64, a, b);
default:
UNREACHABLE();
return U16U32U64{};
}
}
U32U64 IREmitter::FPSqrt(const U32U64& a) {

2
src/frontend/ir/ir_emitter.h
View file

@ -310,7 +310,7 @@ public:
U16U32U64 FPRecipStepFused(const U16U32U64& a, const U16U32U64& b);
U16U32U64 FPRoundInt(const U16U32U64& a, FP::RoundingMode rounding, bool exact);
U16U32U64 FPRSqrtEstimate(const U16U32U64& a);
U32U64 FPRSqrtStepFused(const U32U64& a, const U32U64& b);
U16U32U64 FPRSqrtStepFused(const U16U32U64& a, const U16U32U64& b);
U32U64 FPSqrt(const U32U64& a);
U32U64 FPSub(const U32U64& a, const U32U64& b, bool fpcr_controlled);
U16 FPDoubleToHalf(const U64& a, FP::RoundingMode rounding);

1
src/frontend/ir/microinstruction.cpp
View file

@ -287,6 +287,7 @@ bool Inst::ReadsFromAndWritesToFPSRCumulativeExceptionBits() const {
case Opcode::FPRSqrtEstimate16:
case Opcode::FPRSqrtEstimate32:
case Opcode::FPRSqrtEstimate64:
case Opcode::FPRSqrtStepFused16:
case Opcode::FPRSqrtStepFused32:
case Opcode::FPRSqrtStepFused64:
case Opcode::FPSqrt32:

1
src/frontend/ir/opcodes.inc
View file

@ -506,6 +506,7 @@ OPCODE(FPRoundInt64, U64, U64,
OPCODE(FPRSqrtEstimate16, U16, U16 )
OPCODE(FPRSqrtEstimate32, U32, U32 )
OPCODE(FPRSqrtEstimate64, U64, U64 )
OPCODE(FPRSqrtStepFused16, U16, U16, U16 )
OPCODE(FPRSqrtStepFused32, U32, U32, U32 )
OPCODE(FPRSqrtStepFused64, U64, U64, U64 )
OPCODE(FPSqrt32, U32, U32 )