general: Remove trailing spaces

General code-related cleanup. Gets rid of trailing spaces in the
codebase.

src/backend/x64/a64_interface.cpp

@@ -37,7 +37,7 @@ static RunCodeCallbacks GenRunCodeCallbacks(A64::UserCallbacks* cb, CodePtr (*Lo
 struct Jit::Impl final {
 public:
     Impl(Jit* jit, UserConfig conf)
-        : conf(conf) 
+        : conf(conf)
         , block_of_code(GenRunCodeCallbacks(conf.callbacks, &GetCurrentBlockThunk, this), JitStateInfo{jit_state})
         , emitter(block_of_code, conf, jit)
     {

src/backend/x64/emit_x64_vector.cpp

@@ -3399,7 +3399,7 @@ void EmitX64::EmitVectorSignedSaturatedDoublingMultiply32(EmitContext& ctx, IR::
 
         if (upper_inst) {
             const Xbyak::Xmm upper_result = ctx.reg_alloc.ScratchXmm();
-            
+
             code.vpsrlq(upper_result, odds, 32);
             code.vblendps(upper_result, upper_result, even, 0b1010);
 
@@ -3420,14 +3420,14 @@ void EmitX64::EmitVectorSignedSaturatedDoublingMultiply32(EmitContext& ctx, IR::
 
         if (lower_inst) {
             const Xbyak::Xmm lower_result = ctx.reg_alloc.ScratchXmm();
-            
+
             code.vpsllq(lower_result, even, 32);
             code.vblendps(lower_result, lower_result, odds, 0b0101);
 
             ctx.reg_alloc.DefineValue(lower_inst, lower_result);
             ctx.EraseInstruction(lower_inst);
         }
-        
+
         return;
     }
 

src/common/cast_util.h

@@ -32,7 +32,7 @@ inline Dest BitCastPointee(const SourcePtr source) {
 
     std::aligned_storage_t<sizeof(Dest), alignof(Dest)> dest;
     std::memcpy(&dest, BitCast<void*>(source), sizeof(dest));
-    return reinterpret_cast<Dest&>(dest);    
+    return reinterpret_cast<Dest&>(dest);
 }
 
 } // namespace Dynarmic::Common

src/common/fp/info.h

@@ -114,4 +114,4 @@ constexpr FPT FPValue() {
     return FPT(FPInfo<FPT>::Zero(sign) | mantissa | (biased_exponent << FPInfo<FPT>::explicit_mantissa_width));
 }
 
-} // namespace Dynarmic::FP 
+} // namespace Dynarmic::FP

src/common/fp/mantissa_util.h

@@ -44,4 +44,4 @@ inline ResidualError ResidualErrorOnRightShift(u64 mantissa, int shift_amount) {
     return ResidualError::GreaterThanHalf;
 }
 
-} // namespace Dynarmic::FP 
+} // namespace Dynarmic::FP

src/common/fp/op/FPMulAdd.cpp

@@ -77,4 +77,4 @@ template u16 FPMulAdd<u16>(u16 addend, u16 op1, u16 op2, FPCR fpcr, FPSR& fpsr);
 template u32 FPMulAdd<u32>(u32 addend, u32 op1, u32 op2, FPCR fpcr, FPSR& fpsr);
 template u64 FPMulAdd<u64>(u64 addend, u64 op1, u64 op2, FPCR fpcr, FPSR& fpsr);
 
-} // namespace Dynarmic::FP 
+} // namespace Dynarmic::FP

src/common/fp/op/FPMulAdd.h

@@ -14,4 +14,4 @@ class FPSR;
 template<typename FPT>
 FPT FPMulAdd(FPT addend, FPT op1, FPT op2, FPCR fpcr, FPSR& fpsr);
 
-} // namespace Dynarmic::FP 
+} // namespace Dynarmic::FP

src/common/fp/op/FPNeg.h

@@ -15,4 +15,4 @@ inline FPT FPNeg(FPT op) {
     return op ^ FPInfo<FPT>::sign_mask;
 }
 
-} // namespace Dynarmic::FP 
+} // namespace Dynarmic::FP

src/common/fp/op/FPRSqrtEstimate.cpp

@@ -54,4 +54,4 @@ template u16 FPRSqrtEstimate<u16>(u16 op, FPCR fpcr, FPSR& fpsr);
 template u32 FPRSqrtEstimate<u32>(u32 op, FPCR fpcr, FPSR& fpsr);
 template u64 FPRSqrtEstimate<u64>(u64 op, FPCR fpcr, FPSR& fpsr);
 
-} // namespace Dynarmic::FP 
+} // namespace Dynarmic::FP

src/common/fp/op/FPRSqrtEstimate.h

@@ -14,4 +14,4 @@ class FPSR;
 template<typename FPT>
 FPT FPRSqrtEstimate(FPT op, FPCR fpcr, FPSR& fpsr);
 
-} // namespace Dynarmic::FP 
+} // namespace Dynarmic::FP

src/common/fp/op/FPRSqrtStepFused.cpp

@@ -54,4 +54,4 @@ template u16 FPRSqrtStepFused<u16>(u16 op1, u16 op2, FPCR fpcr, FPSR& fpsr);
 template u32 FPRSqrtStepFused<u32>(u32 op1, u32 op2, FPCR fpcr, FPSR& fpsr);
 template u64 FPRSqrtStepFused<u64>(u64 op1, u64 op2, FPCR fpcr, FPSR& fpsr);
 
-} // namespace Dynarmic::FP 
+} // namespace Dynarmic::FP

src/common/fp/op/FPRSqrtStepFused.h

@@ -14,4 +14,4 @@ class FPSR;
 template<typename FPT>
 FPT FPRSqrtStepFused(FPT op1, FPT op2, FPCR fpcr, FPSR& fpsr);
 
-} // namespace Dynarmic::FP 
+} // namespace Dynarmic::FP

src/common/fp/op/FPRecipEstimate.cpp

@@ -97,4 +97,4 @@ template u16 FPRecipEstimate<u16>(u16 op, FPCR fpcr, FPSR& fpsr);
 template u32 FPRecipEstimate<u32>(u32 op, FPCR fpcr, FPSR& fpsr);
 template u64 FPRecipEstimate<u64>(u64 op, FPCR fpcr, FPSR& fpsr);
 
-} // namespace Dynarmic::FP 
+} // namespace Dynarmic::FP

src/common/fp/op/FPRecipEstimate.h

@@ -14,4 +14,4 @@ class FPSR;
 template<typename FPT>
 FPT FPRecipEstimate(FPT op, FPCR fpcr, FPSR& fpsr);
 
-} // namespace Dynarmic::FP 
+} // namespace Dynarmic::FP

src/common/fp/op/FPRecipStepFused.cpp

@@ -53,4 +53,4 @@ template u16 FPRecipStepFused<u16>(u16 op1, u16 op2, FPCR fpcr, FPSR& fpsr);
 template u32 FPRecipStepFused<u32>(u32 op1, u32 op2, FPCR fpcr, FPSR& fpsr);
 template u64 FPRecipStepFused<u64>(u64 op1, u64 op2, FPCR fpcr, FPSR& fpsr);
 
-} // namespace Dynarmic::FP 
+} // namespace Dynarmic::FP

src/common/fp/op/FPRecipStepFused.h

@@ -14,4 +14,4 @@ class FPSR;
 template<typename FPT>
 FPT FPRecipStepFused(FPT op1, FPT op2, FPCR fpcr, FPSR& fpsr);
 
-} // namespace Dynarmic::FP 
+} // namespace Dynarmic::FP

src/common/fp/op/FPRoundInt.cpp

@@ -33,7 +33,7 @@ u64 FPRoundInt(FPT op, FPCR fpcr, RoundingMode rounding, bool exact, FPSR& fpsr)
     if (type == FPType::Infinity) {
         return FPInfo<FPT>::Infinity(sign);
     }
-    
+
     if (type == FPType::Zero) {
         return FPInfo<FPT>::Zero(sign);
     }
@@ -93,4 +93,4 @@ template u64 FPRoundInt<u16>(u16 op, FPCR fpcr, RoundingMode rounding, bool exac
 template u64 FPRoundInt<u32>(u32 op, FPCR fpcr, RoundingMode rounding, bool exact, FPSR& fpsr);
 template u64 FPRoundInt<u64>(u64 op, FPCR fpcr, RoundingMode rounding, bool exact, FPSR& fpsr);
 
-} // namespace Dynarmic::FP 
+} // namespace Dynarmic::FP

src/common/fp/op/FPRoundInt.h

@@ -17,4 +17,4 @@ enum class RoundingMode;
 template<typename FPT>
 u64 FPRoundInt(FPT op, FPCR fpcr, RoundingMode rounding, bool exact, FPSR& fpsr);
 
-} // namespace Dynarmic::FP 
+} // namespace Dynarmic::FP

src/common/fp/op/FPToFixed.cpp

@@ -99,4 +99,4 @@ template u64 FPToFixed<u16>(size_t ibits, u16 op, size_t fbits, bool unsigned_,
 template u64 FPToFixed<u32>(size_t ibits, u32 op, size_t fbits, bool unsigned_, FPCR fpcr, RoundingMode rounding, FPSR& fpsr);
 template u64 FPToFixed<u64>(size_t ibits, u64 op, size_t fbits, bool unsigned_, FPCR fpcr, RoundingMode rounding, FPSR& fpsr);
 
-} // namespace Dynarmic::FP 
+} // namespace Dynarmic::FP

src/common/fp/op/FPToFixed.h

@@ -17,4 +17,4 @@ enum class RoundingMode;
 template<typename FPT>
 u64 FPToFixed(size_t ibits, FPT op, size_t fbits, bool unsigned_, FPCR fpcr, RoundingMode rounding, FPSR& fpsr);
 
-} // namespace Dynarmic::FP 
+} // namespace Dynarmic::FP

src/common/fp/process_exception.cpp

@@ -55,4 +55,4 @@ void FPProcessException(FPExc exception, FPCR fpcr, FPSR& fpsr) {
     }
 }
 
-} // namespace Dynarmic::FP 
+} // namespace Dynarmic::FP

src/common/fp/process_exception.h

@@ -22,4 +22,4 @@ enum class FPExc {
 
 void FPProcessException(FPExc exception, FPCR fpcr, FPSR& fpsr);
 
-} // namespace Dynarmic::FP 
+} // namespace Dynarmic::FP

src/common/fp/process_nan.cpp

@@ -89,4 +89,4 @@ template std::optional<u16> FPProcessNaNs3<u16>(FPType type1, FPType type2, FPTy
 template std::optional<u32> FPProcessNaNs3<u32>(FPType type1, FPType type2, FPType type3, u32 op1, u32 op2, u32 op3, FPCR fpcr, FPSR& fpsr);
 template std::optional<u64> FPProcessNaNs3<u64>(FPType type1, FPType type2, FPType type3, u64 op1, u64 op2, u64 op3, FPCR fpcr, FPSR& fpsr);
 
-} // namespace Dynarmic::FP 
+} // namespace Dynarmic::FP

src/common/fp/process_nan.h

@@ -23,4 +23,4 @@ std::optional<FPT> FPProcessNaNs(FPType type1, FPType type2, FPT op1, FPT op2, F
 template<typename FPT>
 std::optional<FPT> FPProcessNaNs3(FPType type1, FPType type2, FPType type3, FPT op1, FPT op2, FPT op3, FPCR fpcr, FPSR& fpsr);
 
-} // namespace Dynarmic::FP 
+} // namespace Dynarmic::FP

src/common/mp/cartesian_product.h

@@ -43,7 +43,7 @@ struct cartesian_product_impl<RL, L1, L2, Ls...> {
 } // namespace detail
 
 /// Produces the cartesian product of a set of lists
-/// For example: 
+/// For example:
 /// cartesian_product<list<A, B>, list<D, E>> == list<list<A, D>, list<A, E>, list<B, D>, list<B, E>
 template<typename L1, typename... Ls>
 using cartesian_product = typename detail::cartesian_product_impl<fmap<list, L1>, Ls...>::type;

src/frontend/A32/translate/translate_arm/vfp.cpp

@@ -765,7 +765,7 @@ bool ArmTranslatorVisitor::vfp_VSTM_a1(Cond cond, bool p, bool u, bool D, bool w
     if (!p && !u && !w) {
         ASSERT_MSG(false, "Decode error");
     }
-    
+
     if (p && !w) {
         ASSERT_MSG(false, "Decode error");
     }

src/frontend/A64/translate/impl/data_processing_register.cpp

@@ -34,17 +34,17 @@ bool TranslatorVisitor::RBIT_int(bool sf, Reg Rn, Reg Rd) {
         const IR::U32 first_lsl = ir.LogicalShiftLeft(ir.And(operand, ir.Imm32(0x55555555)), ir.Imm8(1));
         const IR::U32 first_lsr = ir.And(ir.LogicalShiftRight(operand, ir.Imm8(1)), ir.Imm32(0x55555555));
         const IR::U32 first = ir.Or(first_lsl, first_lsr);
-        
+
         // x = (x & 0x33333333) << 2 | ((x >> 2) & 0x33333333);
         const IR::U32 second_lsl = ir.LogicalShiftLeft(ir.And(first, ir.Imm32(0x33333333)), ir.Imm8(2));
         const IR::U32 second_lsr = ir.And(ir.LogicalShiftRight(first, ir.Imm8(2)), ir.Imm32(0x33333333));
         const IR::U32 second = ir.Or(second_lsl, second_lsr);
-        
+
         // x = (x & 0x0F0F0F0F) << 4 | ((x >> 4) & 0x0F0F0F0F);
         const IR::U32 third_lsl = ir.LogicalShiftLeft(ir.And(second, ir.Imm32(0x0F0F0F0F)), ir.Imm8(4));
         const IR::U32 third_lsr = ir.And(ir.LogicalShiftRight(second, ir.Imm8(4)), ir.Imm32(0x0F0F0F0F));
         const IR::U32 third = ir.Or(third_lsl, third_lsr);
-        
+
         // x = (x << 24) | ((x & 0xFF00) << 8) | ((x >> 8) & 0xFF00) | (x >> 24);
         const IR::U32 fourth_lsl = ir.Or(ir.LogicalShiftLeft(third, ir.Imm8(24)),
                                          ir.LogicalShiftLeft(ir.And(third, ir.Imm32(0xFF00)), ir.Imm8(8)));

src/frontend/A64/translate/impl/load_store_register_register_offset.cpp

@@ -67,7 +67,7 @@ static bool RegSharedDecodeAndOperation(TranslatorVisitor& v, size_t scale, u8 s
     case MemOp::PREFETCH:
         // TODO: Prefetch
         break;
-    default: 
+    default:
         UNREACHABLE();
     }
 

src/frontend/A64/translate/impl/simd_across_lanes.cpp

@@ -89,7 +89,7 @@ bool FPMinMax(TranslatorVisitor& v, bool Q, bool sz, Vec Vn, Vec Vd, MinMaxOpera
 
         for (size_t i = start + 1; i < end; i++) {
             const IR::U32U64 element = v.ir.VectorGetElement(esize, operand, i);
- 
+
             result = op(result, element);
         }
 
@@ -128,7 +128,7 @@ bool ScalarMinMax(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vn, Vec Vd,
 
         return v.ir.ZeroExtendToWord(vec_element);
     };
-    
+
     const auto op_func = [&](const auto& a, const auto& b) {
         switch (operation) {
         case ScalarMinMaxOperation::Max:

src/frontend/A64/translate/impl/simd_sha512.cpp

@@ -124,7 +124,7 @@ IR::U32 SM4Rotation(IREmitter& ir, IR::U32 intval, IR::U32 round_result_low_word
 IR::U128 SM4Hash(IREmitter& ir, Vec Vn, Vec Vd, SM4RotationType type) {
     const IR::U128 n = ir.GetQ(Vn);
     IR::U128 roundresult = ir.GetQ(Vd);
-    
+
     for (size_t i = 0; i < 4; i++) {
         const IR::U32 round_key = ir.VectorGetElement(32, n, i);
 

src/frontend/A64/translate/impl/simd_three_different.cpp

@@ -90,7 +90,7 @@ enum class LongOperationBehavior {
     Addition,
     Subtraction
 };
-    
+
 bool LongOperation(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd,
                    LongOperationBehavior behavior, Signedness sign) {
     if (size == 0b11) {

src/frontend/A64/translate/impl/simd_two_register_misc.cpp

@@ -99,7 +99,7 @@ bool IntegerConvertToFloat(TranslatorVisitor& v, bool Q, bool sz, Vec Vn, Vec Vd
 
     const IR::U128 operand = v.V(datasize, Vn);
     const IR::U128 result = signedness == Signedness::Signed
-                          ? v.ir.FPVectorFromSignedFixed(esize, operand, 0, rounding_mode) 
+                          ? v.ir.FPVectorFromSignedFixed(esize, operand, 0, rounding_mode)
                           : v.ir.FPVectorFromUnsignedFixed(esize, operand, 0, rounding_mode);
 
     v.V(datasize, Vd, result);

src/frontend/A64/translate/impl/simd_vector_x_indexed_element.cpp

@@ -96,7 +96,7 @@ bool FPMultiplyByElementHalfPrecision(TranslatorVisitor& v, bool Q, Imm<1> L, Im
     const Vec Vm = Vmlo.ZeroExtend<Vec>();
     const size_t esize = 16;
     const size_t datasize = Q ? 128 : 64;
-    
+
     const IR::UAny element2 = v.ir.VectorGetElement(esize, v.V(idxdsize, Vm), index);
     const IR::U128 operand1 = v.V(datasize, Vn);
     const IR::U128 operand2 = Q ? v.ir.VectorBroadcast(esize, element2) : v.ir.VectorBroadcastLower(esize, element2);

src/frontend/A64/types.h

@@ -20,7 +20,7 @@ using Cond = IR::Cond;
 
 enum class Reg {
     R0, R1, R2, R3, R4, R5, R6, R7,
-    R8, R9, R10, R11, R12, R13, R14, R15, 
+    R8, R9, R10, R11, R12, R13, R14, R15,
     R16, R17, R18, R19, R20, R21, R22, R23,
     R24, R25, R26, R27, R28, R29, R30, R31,
     LR = R30,
@@ -29,7 +29,7 @@ enum class Reg {
 
 enum class Vec {
     V0, V1, V2, V3, V4, V5, V6, V7,
-    V8, V9, V10, V11, V12, V13, V14, V15, 
+    V8, V9, V10, V11, V12, V13, V14, V15,
     V16, V17, V18, V19, V20, V21, V22, V23,
     V24, V25, V26, V27, V28, V29, V30, V31,
 };

src/ir_opt/constant_propagation_pass.cpp

@@ -126,7 +126,7 @@ void FoldLeastSignificantByte(IR::Inst& inst) {
     if (!inst.AreAllArgsImmediates()) {
         return;
     }
-    
+
     const auto operand = inst.GetArg(0);
     inst.ReplaceUsesWith(IR::Value{static_cast<u8>(operand.GetImmediateAsU64())});
 }