Implement thumb1_AND_reg

src/backend_x64/emit_x64.cpp

@@ -436,6 +436,15 @@ void EmitX64::EmitAddWithCarry(IR::Value* value_) {
     }
 }
 
+void EmitX64::EmitAnd(IR::Value* value_) {
+    auto value = reinterpret_cast<IR::Inst*>(value_);
+
+    X64Reg andend = reg_alloc.UseRegister(value->GetArg(1).get());
+    X64Reg result = reg_alloc.UseDefRegister(value->GetArg(0).get(), value);
+
+    code->AND(32, R(result), R(andend));
+}
+
 void EmitX64::EmitAddCycles(size_t cycles) {
     ASSERT(cycles < std::numeric_limits<u32>::max());
     code->SUB(64, MDisp(R15, offsetof(JitState, cycles_remaining)), Imm32(static_cast<u32>(cycles)));

src/backend_x64/emit_x64.h

@@ -53,6 +53,7 @@ public:
     void EmitLogicalShiftRight(IR::Value* value);
     void EmitArithmeticShiftRight(IR::Value* value);
     void EmitAddWithCarry(IR::Value* value);
+    void EmitAnd(IR::Value* value);
 
     void EmitAddCycles(size_t cycles);
 

src/frontend/decoder/thumb1.h

@@ -56,7 +56,7 @@ private:
 };
 
 template <typename V>
-static const std::array<Thumb1Matcher<V>, 9> g_thumb1_instruction_table {{
+static const std::array<Thumb1Matcher<V>, 10> g_thumb1_instruction_table {{
 
 #define INST(fn, name, bitstring) detail::detail<Thumb1Matcher, u16, 16>::GetMatcher<decltype(fn), fn>(name, bitstring)
 
@@ -74,7 +74,7 @@ static const std::array<Thumb1Matcher<V>, 9> g_thumb1_instruction_table {{
     //{ INST(&V::thumb1_SUB_ri,         "SUB (ri)",                 "00111dddvvvvvvvv") },
 
      // Data-processing instructions
-//    { INST(&V::thumb1_AND_reg,        "AND (reg)",                "0100000000mmmddd") },
+    { INST(&V::thumb1_AND_reg,        "AND (reg)",                "0100000000mmmddd") },
 //    { INST(&V::thumb1_EOR_reg,        "EOR (reg)",                "0100000001mmmddd") },
     { INST(&V::thumb1_LSL_reg,        "LSL (reg)",                "0100000010mmmddd") },
     { INST(&V::thumb1_LSR_reg,        "LSR (reg)",                "0100000011mmmddd") },

src/frontend/disassembler_thumb.cpp

@@ -118,6 +118,10 @@ public:
         return Common::StringFromFormat("adds %s, %s, %s", RegStr(d), RegStr(n), RegStr(m));
     }
 
+    std::string thumb1_AND_reg(Reg m, Reg d_n) {
+        return Common::StringFromFormat("ands %s, %s", RegStr(d_n), RegStr(m));
+    }
+
     std::string thumb1_LSL_reg(Reg m, Reg d_n) {
         return Common::StringFromFormat("lsls %s, %s", RegStr(d_n), RegStr(m));
     }

src/frontend/ir/opcodes.inc

@@ -30,3 +30,4 @@ OPCODE(LogicalShiftLeft,        T::U32,         T::U32,         T::U8,
 OPCODE(LogicalShiftRight,       T::U32,         T::U32,         T::U8,          T::U1           )
 OPCODE(ArithmeticShiftRight,    T::U32,         T::U32,         T::U8,          T::U1           )
 OPCODE(AddWithCarry,            T::U32,         T::U32,         T::U32,         T::U1           )
+OPCODE(And,                     T::U32,         T::U32,         T::U32                          )

src/frontend/ir_emitter.cpp

@@ -106,6 +106,10 @@ IREmitter::ResultAndCarryAndOverflow IREmitter::AddWithCarry(IR::ValuePtr a, IR:
     return {result, carry_out, overflow};
 }
 
+IR::ValuePtr IREmitter::And(IR::ValuePtr a, IR::ValuePtr b) {
+    return Inst(IR::Opcode::And, {a, b});
+}
+
 void IREmitter::SetTerm(const IR::Terminal& terminal) {
     ASSERT_MSG(block.terminal.which() == 0, "Terminal has already been set.");
     block.terminal = terminal;

src/frontend/ir_emitter.h

@@ -56,6 +56,7 @@ public:
     ResultAndCarry LogicalShiftRight(IR::ValuePtr value_in, IR::ValuePtr shift_amount, IR::ValuePtr carry_in);
     ResultAndCarry ArithmeticShiftRight(IR::ValuePtr value_in, IR::ValuePtr shift_amount, IR::ValuePtr carry_in);
     ResultAndCarryAndOverflow AddWithCarry(IR::ValuePtr a, IR::ValuePtr b, IR::ValuePtr carry_in);
+    IR::ValuePtr And(IR::ValuePtr a, IR::ValuePtr b);
 
     void SetTerm(const IR::Terminal& terminal);
 

src/frontend/translate_thumb.cpp

@@ -76,6 +76,16 @@ struct TranslatorVisitor final {
         return true;
     }
 
+    bool thumb1_AND_reg(Reg m, Reg d_n) {
+        const Reg d = d_n, n = d_n;
+        // ANDS <Rdn>, <Rm>
+        // Note that it is not possible to encode Rdn == R15.
+        auto result = ir.And(ir.GetRegister(n), ir.GetRegister(m));
+        ir.SetRegister(d, result);
+        ir.SetNFlag(ir.MostSignificantBit(result));
+        ir.SetZFlag(ir.IsZero(result));
+        return true;
+    }
     bool thumb1_LSL_reg(Reg m, Reg d_n) {
         const Reg d = d_n, n = d_n;
         // LSLS <Rdn>, <Rm>

tests/arm/fuzz_thumb.cpp

@@ -210,7 +210,7 @@ TEST_CASE("Fuzz Thumb instructions set 1", "[JitX64][Thumb]") {
     };
 
     SECTION("short blocks") {
-        FuzzJitThumb(5, 6, 100, instruction_select);
+        FuzzJitThumb(5, 6, 300, instruction_select);
     }
 
     SECTION("long blocks") {