backend/EmitX64: Handle new_pc<1:0> == '10' case in BXWritePC
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14dcb18bbe
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8a310777a1
1 changed files with 20 additions and 23 deletions
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@ -222,32 +222,29 @@ void EmitX64::EmitBXWritePC(IR::Value* value_) {
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auto value = reinterpret_cast<IR::Inst*>(value_);
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X64Reg new_pc = reg_alloc.UseRegister(value->GetArg(0).get());
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X64Reg tmp = reg_alloc.ScratchRegister();
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X64Reg cpsr = reg_alloc.ScratchRegister();
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X64Reg tmp1 = reg_alloc.ScratchRegister();
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X64Reg tmp2 = reg_alloc.ScratchRegister();
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// Note: new_pc<1:0> == '10' is UNPREDICTABLE
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// Pseudocode:
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// if (new_pc & 1) {
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// new_pc &= 0xFFFFFFFE;
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// cpsr.T = true;
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// } else {
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// new_pc &= 0xFFFFFFFC;
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// cpsr.T = false;
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// }
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// Alternative implementations
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#if 0
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code->MOV(32, R(tmp), MJitStateCpsr());
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code->MOV(32, R(cpsr), R(tmp));
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code->OR(32, R(tmp), Imm32(1 << 5));
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code->AND(32, R(cpsr), Imm32(~(1 << 5)));
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code->BTR(32, R(new_pc), Imm8(0));
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code->CMOVcc(32, cpsr, R(tmp), CC_C);
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code->MOV(32, R(tmp1), MJitStateCpsr());
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code->MOV(32, R(tmp2), R(tmp1));
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code->AND(32, R(tmp2), Imm32(~(1 << 5))); // CPSR.T = 0
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code->OR(32, R(tmp1), Imm32(1 << 5)); // CPSR.T = 1
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code->TEST(8, R(new_pc), Imm8(1));
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code->CMOVcc(32, tmp1, R(tmp2), CC_E); // CPSR.T = pc & 1
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code->MOV(32, MJitStateCpsr(), R(tmp1));
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code->LEA(32, tmp2, MComplex(new_pc, new_pc, 1, 0));
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code->OR(32, R(tmp2), Imm32(0xFFFFFFFC)); // tmp2 = pc & 1 ? 0xFFFFFFFE : 0xFFFFFFFC
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code->AND(32, R(new_pc), R(tmp2));
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code->MOV(32, MJitStateReg(Arm::Reg::PC), R(new_pc));
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code->MOV(32, MJitStateCpsr(), R(cpsr));
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#else
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code->MOV(32, R(tmp), R(new_pc));
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code->AND(32, R(tmp), Imm8(1));
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code->AND(32, R(new_pc), Imm32(0xFFFFFFFE));
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code->MOV(32, R(cpsr), MJitStateCpsr());
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code->SHL(32, R(tmp), Imm8(5));
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code->AND(32, R(cpsr), Imm32(~(1 << 5)));
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code->OR(32, R(cpsr), R(tmp));
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code->MOV(32, MJitStateReg(Arm::Reg::PC), R(new_pc));
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code->MOV(32, MJitStateCpsr(), R(cpsr));
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#endif
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}
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void EmitX64::EmitCallSupervisor(IR::Value* value_) {
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