A32: Implement ARM-mode MOVT

src/frontend/A32/decoder/arm.inc

@@ -167,6 +167,7 @@ INST(arm_STM_usr,       "STM (usr reg)",       "----100--100--------------------
 INST(arm_BFC,           "BFC",                 "cccc0111110vvvvvddddvvvvv0011111") // v6T2
 INST(arm_BFI,           "BFI",                 "cccc0111110vvvvvddddvvvvv001nnnn") // v6T2
 INST(arm_CLZ,           "CLZ",                 "cccc000101101111dddd11110001mmmm") // v5
+INST(arm_MOVT,          "MOVT",                "cccc00110100vvvvddddvvvvvvvvvvvv") // v6T2
 INST(arm_NOP,           "NOP",                 "----0011001000001111000000000000") // v6K
 INST(arm_SBFX,          "SBFX",                "cccc0111101wwwwwddddvvvvv101nnnn") // v6T2
 INST(arm_SEL,           "SEL",                 "cccc01101000nnnndddd11111011mmmm") // v6

src/frontend/A32/disassembler/disassembler_arm.cpp

@@ -592,6 +592,9 @@ public:
     std::string arm_CLZ(Cond cond, Reg d, Reg m) {
         return fmt::format("clz{} {}, {}", CondToString(cond), d, m);
     }
+    std::string arm_MOVT(Cond cond, Imm4 imm4, Reg d, Imm12 imm12) {
+        return fmt::format("movt{} {}, #{}", CondToString(cond), d, (imm4 << 12) | imm12);
+    }
     std::string arm_NOP() {
         return "nop";
     }

src/frontend/A32/translate/translate_arm/misc.cpp

@@ -67,6 +67,24 @@ bool ArmTranslatorVisitor::arm_CLZ(Cond cond, Reg d, Reg m) {
     return true;
 }
 
+// MOVT<c> <Rd>, #<imm16>
+bool ArmTranslatorVisitor::arm_MOVT(Cond cond, Imm4 imm4, Reg d, Imm12 imm12) {
+    if (d == Reg::PC) {
+        return UnpredictableInstruction();
+    }
+
+    if (!ConditionPassed(cond)) {
+        return true;
+    }
+
+    const IR::U32 imm16 = ir.Imm32(((u32(imm4) << 12 | u32(imm12)) << 16));
+    const IR::U32 operand = ir.GetRegister(d);
+    const IR::U32 result = ir.Or(ir.And(operand, ir.Imm32(0x0000FFFFU)), imm16);
+
+    ir.SetRegister(d, result);
+    return true;
+}
+
 // SBFX<c> <Rd>, <Rn>, #<lsb>, #<width>
 bool ArmTranslatorVisitor::arm_SBFX(Cond cond, Imm5 widthm1, Reg d, Imm5 lsb, Reg n) {
     if (d == Reg::PC || n == Reg::PC) {

src/frontend/A32/translate/translate_arm/translate_arm.h

@@ -210,6 +210,7 @@ struct ArmTranslatorVisitor final {
     bool arm_BFC(Cond cond, Imm5 msb, Reg d, Imm5 lsb);
     bool arm_BFI(Cond cond, Imm5 msb, Reg d, Imm5 lsb, Reg n);
     bool arm_CLZ(Cond cond, Reg d, Reg m);
+    bool arm_MOVT(Cond cond, Imm4 imm4, Reg d, Imm12 imm12);
     bool arm_NOP() { return true; }
     bool arm_RBIT(Cond cond, Reg d, Reg m);
     bool arm_SBFX(Cond cond, Imm5 widthm1, Reg d, Imm5 lsb, Reg n);

tests/A32/fuzz_arm.cpp

@@ -1103,11 +1103,15 @@ TEST_CASE("Test ARM misc instructions", "[JitX64][A32]") {
                Bits<12, 15>(instr) != 0b1111 &&
                msb < Dynarmic::Common::BitSize<u32>();
     };
+    const auto is_movt_valid = [](u32 instr) {
+        return Bits<12, 15>(instr) != 0b1111;
+    };
 
     const std::array instructions = {
         InstructionGenerator("cccc0111110vvvvvddddvvvvv0011111", is_bfc_bfi_valid), // BFC
         InstructionGenerator("cccc0111110vvvvvddddvvvvv001nnnn", is_bfc_bfi_valid), // BFI
         InstructionGenerator("cccc000101101111dddd11110001mmmm", is_clz_valid),     // CLZ
+        InstructionGenerator("cccc00110100vvvvddddvvvvvvvvvvvv", is_movt_valid),    // MOVT
         InstructionGenerator("cccc0111101wwwwwddddvvvvv101nnnn", is_extract_valid), // SBFX
         InstructionGenerator("cccc0111111wwwwwddddvvvvv101nnnn", is_extract_valid), // UBFX
     };