A64: Implement UADDW

This commit is contained in:
MerryMage 2018-04-02 21:15:51 +01:00
parent 5c47f03888
commit 8bba37089e
4 changed files with 31 additions and 2 deletions

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@ -108,6 +108,7 @@ add_library(dynarmic
frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp
frontend/A64/translate/impl/simd_sha.cpp frontend/A64/translate/impl/simd_sha.cpp
frontend/A64/translate/impl/simd_shift_by_immediate.cpp frontend/A64/translate/impl/simd_shift_by_immediate.cpp
frontend/A64/translate/impl/simd_three_different.cpp
frontend/A64/translate/impl/simd_three_same.cpp frontend/A64/translate/impl/simd_three_same.cpp
frontend/A64/translate/impl/simd_two_register_misc.cpp frontend/A64/translate/impl/simd_two_register_misc.cpp
frontend/A64/translate/impl/sys_dc.cpp frontend/A64/translate/impl/sys_dc.cpp

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@ -688,7 +688,7 @@ INST(NOT, "NOT", "0Q101
//INST(SMULL_vec, "SMULL, SMULL2 (vector)", "0Q001110zz1mmmmm110000nnnnnddddd") //INST(SMULL_vec, "SMULL, SMULL2 (vector)", "0Q001110zz1mmmmm110000nnnnnddddd")
//INST(PMULL, "PMULL, PMULL2", "0Q001110zz1mmmmm111000nnnnnddddd") //INST(PMULL, "PMULL, PMULL2", "0Q001110zz1mmmmm111000nnnnnddddd")
//INST(UADDL, "UADDL, UADDL2", "0Q101110zz1mmmmm000000nnnnnddddd") //INST(UADDL, "UADDL, UADDL2", "0Q101110zz1mmmmm000000nnnnnddddd")
//INST(UADDW, "UADDW, UADDW2", "0Q101110zz1mmmmm000100nnnnnddddd") INST(UADDW, "UADDW, UADDW2", "0Q101110zz1mmmmm000100nnnnnddddd")
//INST(USUBL, "USUBL, USUBL2", "0Q101110zz1mmmmm001000nnnnnddddd") //INST(USUBL, "USUBL, USUBL2", "0Q101110zz1mmmmm001000nnnnnddddd")
//INST(USUBW, "USUBW, USUBW2", "0Q101110zz1mmmmm001100nnnnnddddd") //INST(USUBW, "USUBW, USUBW2", "0Q101110zz1mmmmm001100nnnnnddddd")
//INST(RADDHN, "RADDHN, RADDHN2", "0Q101110zz1mmmmm010000nnnnnddddd") //INST(RADDHN, "RADDHN, RADDHN2", "0Q101110zz1mmmmm010000nnnnnddddd")

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@ -815,7 +815,7 @@ struct TranslatorVisitor final {
bool SMULL_vec(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd); bool SMULL_vec(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd);
bool PMULL(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd); bool PMULL(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd);
bool UADDL(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd); bool UADDL(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd);
bool UADDW(bool Q, Imm<2> size, Reg Rm, Vec Vn, Vec Vd); bool UADDW(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
bool USUBL(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd); bool USUBL(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd);
bool USUBW(bool Q, Imm<2> size, Reg Rm, Vec Vn, Vec Vd); bool USUBW(bool Q, Imm<2> size, Reg Rm, Vec Vn, Vec Vd);
bool RADDHN(bool Q, Imm<2> size, Vec Vm, Vec Vn, Reg Rd); bool RADDHN(bool Q, Imm<2> size, Vec Vm, Vec Vn, Reg Rd);

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@ -0,0 +1,28 @@
/* This file is part of the dynarmic project.
* Copyright (c) 2018 MerryMage
* This software may be used and distributed according to the terms of the GNU
* General Public License version 2 or any later version.
*/
#include "frontend/A64/translate/impl/impl.h"
namespace Dynarmic::A64 {
bool TranslatorVisitor::UADDW(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
if (size == 0b11) {
return ReservedValue();
}
const size_t esize = 8 << size.ZeroExtend<size_t>();
const size_t part = Q ? 1 : 0;
const IR::U128 operand1 = V(128, Vn);
const IR::U128 operand2 = ir.VectorZeroExtend(esize, Vpart(64, Vm, part));
const IR::U128 result = ir.VectorAdd(esize * 2, operand1, operand2);
V(128, Vd, result);
return true;
}
} // namespace Dynarmic::A64