A64: Implement UADDW
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parent
5c47f03888
commit
8bba37089e
4 changed files with 31 additions and 2 deletions
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@ -108,6 +108,7 @@ add_library(dynarmic
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frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp
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frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp
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frontend/A64/translate/impl/simd_sha.cpp
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frontend/A64/translate/impl/simd_sha.cpp
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frontend/A64/translate/impl/simd_shift_by_immediate.cpp
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frontend/A64/translate/impl/simd_shift_by_immediate.cpp
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frontend/A64/translate/impl/simd_three_different.cpp
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frontend/A64/translate/impl/simd_three_same.cpp
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frontend/A64/translate/impl/simd_three_same.cpp
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frontend/A64/translate/impl/simd_two_register_misc.cpp
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frontend/A64/translate/impl/simd_two_register_misc.cpp
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frontend/A64/translate/impl/sys_dc.cpp
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frontend/A64/translate/impl/sys_dc.cpp
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@ -688,7 +688,7 @@ INST(NOT, "NOT", "0Q101
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//INST(SMULL_vec, "SMULL, SMULL2 (vector)", "0Q001110zz1mmmmm110000nnnnnddddd")
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//INST(SMULL_vec, "SMULL, SMULL2 (vector)", "0Q001110zz1mmmmm110000nnnnnddddd")
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//INST(PMULL, "PMULL, PMULL2", "0Q001110zz1mmmmm111000nnnnnddddd")
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//INST(PMULL, "PMULL, PMULL2", "0Q001110zz1mmmmm111000nnnnnddddd")
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//INST(UADDL, "UADDL, UADDL2", "0Q101110zz1mmmmm000000nnnnnddddd")
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//INST(UADDL, "UADDL, UADDL2", "0Q101110zz1mmmmm000000nnnnnddddd")
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//INST(UADDW, "UADDW, UADDW2", "0Q101110zz1mmmmm000100nnnnnddddd")
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INST(UADDW, "UADDW, UADDW2", "0Q101110zz1mmmmm000100nnnnnddddd")
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//INST(USUBL, "USUBL, USUBL2", "0Q101110zz1mmmmm001000nnnnnddddd")
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//INST(USUBL, "USUBL, USUBL2", "0Q101110zz1mmmmm001000nnnnnddddd")
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//INST(USUBW, "USUBW, USUBW2", "0Q101110zz1mmmmm001100nnnnnddddd")
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//INST(USUBW, "USUBW, USUBW2", "0Q101110zz1mmmmm001100nnnnnddddd")
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//INST(RADDHN, "RADDHN, RADDHN2", "0Q101110zz1mmmmm010000nnnnnddddd")
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//INST(RADDHN, "RADDHN, RADDHN2", "0Q101110zz1mmmmm010000nnnnnddddd")
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@ -815,7 +815,7 @@ struct TranslatorVisitor final {
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bool SMULL_vec(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd);
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bool SMULL_vec(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd);
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bool PMULL(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd);
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bool PMULL(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd);
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bool UADDL(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd);
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bool UADDL(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd);
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bool UADDW(bool Q, Imm<2> size, Reg Rm, Vec Vn, Vec Vd);
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bool UADDW(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd);
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bool USUBL(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd);
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bool USUBL(bool Q, Imm<2> size, Reg Rm, Reg Rn, Vec Vd);
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bool USUBW(bool Q, Imm<2> size, Reg Rm, Vec Vn, Vec Vd);
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bool USUBW(bool Q, Imm<2> size, Reg Rm, Vec Vn, Vec Vd);
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bool RADDHN(bool Q, Imm<2> size, Vec Vm, Vec Vn, Reg Rd);
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bool RADDHN(bool Q, Imm<2> size, Vec Vm, Vec Vn, Reg Rd);
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28
src/frontend/A64/translate/impl/simd_three_different.cpp
Normal file
28
src/frontend/A64/translate/impl/simd_three_different.cpp
Normal file
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@ -0,0 +1,28 @@
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/* This file is part of the dynarmic project.
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* Copyright (c) 2018 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#include "frontend/A64/translate/impl/impl.h"
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namespace Dynarmic::A64 {
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bool TranslatorVisitor::UADDW(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
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if (size == 0b11) {
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return ReservedValue();
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}
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const size_t esize = 8 << size.ZeroExtend<size_t>();
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const size_t part = Q ? 1 : 0;
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const IR::U128 operand1 = V(128, Vn);
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const IR::U128 operand2 = ir.VectorZeroExtend(esize, Vpart(64, Vm, part));
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const IR::U128 result = ir.VectorAdd(esize * 2, operand1, operand2);
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V(128, Vd, result);
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return true;
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}
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} // namespace Dynarmic::A64
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