thumb32: Implement ADD (imm, T3)

This commit is contained in:
MerryMage 2021-02-28 19:51:00 +00:00
parent 30442ee1f4
commit 8f9e052c93
3 changed files with 21 additions and 1 deletions

View file

@ -63,7 +63,7 @@ INST(thumb32_ORN_imm, "ORN (imm)", "11110v00011Snnnn0vvvdd
INST(thumb32_TEQ_imm, "TEQ (imm)", "11110v001001nnnn0vvv1111vvvvvvvv")
INST(thumb32_EOR_imm, "EOR (imm)", "11110v00100Snnnn0vvvddddvvvvvvvv")
INST(thumb32_CMN_imm, "CMN (imm)", "11110v010001nnnn0vvv1111vvvvvvvv")
//INST(thumb32_ADD_imm_1, "ADD (imm)", "11110-01000-----0---------------")
INST(thumb32_ADD_imm_1, "ADD (imm)", "11110v01000Snnnn0vvvddddvvvvvvvv")
//INST(thumb32_ADC_imm, "ADC (imm)", "11110-01010-----0---------------")
//INST(thumb32_SBC_imm, "SBC (imm)", "11110-01011-----0---------------")
//INST(thumb32_CMP_imm, "CMP (imm)", "11110-011011----0---1111--------")

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@ -173,4 +173,23 @@ bool ThumbTranslatorVisitor::thumb32_CMN_imm(Imm<1> i, Reg n, Imm<3> imm3, Imm<8
return true;
}
bool ThumbTranslatorVisitor::thumb32_ADD_imm_1(Imm<1> i, bool S, Reg n, Imm<3> imm3, Reg d, Imm<8> imm8) {
ASSERT_MSG(!(d == Reg::PC && S), "Decode error");
if ((d == Reg::PC && !S) || n == Reg::PC) {
return UnpredictableInstruction();
}
const auto imm32 = ThumbExpandImm(i, imm3, imm8);
const auto result = ir.AddWithCarry(ir.GetRegister(n), ir.Imm32(imm32), ir.Imm1(0));
ir.SetRegister(d, result.result);
if (S) {
ir.SetNFlag(ir.MostSignificantBit(result.result));
ir.SetZFlag(ir.IsZero(result.result));
ir.SetCFlag(result.carry);
ir.SetVFlag(result.overflow);
}
return true;
}
} // namespace Dynarmic::A32

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@ -159,6 +159,7 @@ struct ThumbTranslatorVisitor final {
bool thumb32_TEQ_imm(Imm<1> i, Reg n, Imm<3> imm3, Imm<8> imm8);
bool thumb32_EOR_imm(Imm<1> i, bool S, Reg n, Imm<3> imm3, Reg d, Imm<8> imm8);
bool thumb32_CMN_imm(Imm<1> i, Reg n, Imm<3> imm3, Imm<8> imm8);
bool thumb32_ADD_imm_1(Imm<1> i, bool S, Reg n, Imm<3> imm3, Reg d, Imm<8> imm8);
// thumb32 data processing (plain binary immediate) instructions.
bool thumb32_MOVT(Imm<1> imm1, Imm<4> imm4, Imm<3> imm3, Reg d, Imm<8> imm8);