emit_x64_floating_point: AVX implementation of ForceToDefaultNaN
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dfb660cd16
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90f8dda966
1 changed files with 15 additions and 10 deletions
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@ -176,12 +176,17 @@ void PostProcessNaNs(BlockOfCode& code, Xbyak::Xmm result, Xbyak::Xmm tmp) {
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}
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template<size_t fsize>
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void DefaultNaN(BlockOfCode& code, Xbyak::Xmm xmm_value) {
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void ForceToDefaultNaN(BlockOfCode& code, Xbyak::Xmm result) {
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
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FCODE(vcmpunords)(xmm0, result, result);
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FCODE(blendvp)(result, code.MConst(xword, fsize == 32 ? f32_nan : f64_nan));
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} else {
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Xbyak::Label end;
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FCODE(ucomis)(xmm_value, xmm_value);
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FCODE(ucomis)(result, result);
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code.jnp(end);
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code.movaps(xmm_value, code.MConst(xword, fsize == 32 ? f32_nan : f64_nan));
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code.movaps(result, code.MConst(xword, fsize == 32 ? f32_nan : f64_nan));
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code.L(end);
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}
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}
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template<size_t fsize>
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@ -217,7 +222,7 @@ void FPTwoOp(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, Function fn) {
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fn(result);
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}
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if (ctx.FPSCR_DN()) {
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DefaultNaN<fsize>(code, result);
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ForceToDefaultNaN<fsize>(code, result);
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} else if (ctx.AccurateNaN()) {
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PostProcessNaNs<fsize>(code, result, ctx.reg_alloc.ScratchXmm());
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}
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@ -257,7 +262,7 @@ void FPThreeOp(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, [[maybe_unus
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fn(result, operand);
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}
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if (ctx.FPSCR_DN()) {
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DefaultNaN<fsize>(code, result);
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ForceToDefaultNaN<fsize>(code, result);
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} else if (ctx.AccurateNaN()) {
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PostProcessNaNs<fsize>(code, result, operand);
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}
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@ -899,7 +904,7 @@ void EmitX64::EmitFPSingleToDouble(EmitContext& ctx, IR::Inst* inst) {
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}
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code.cvtss2sd(result, result);
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if (ctx.FPSCR_DN()) {
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DefaultNaN<64>(code, result);
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ForceToDefaultNaN<64>(code, result);
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}
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ctx.reg_alloc.DefineValue(inst, result);
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@ -915,7 +920,7 @@ void EmitX64::EmitFPDoubleToSingle(EmitContext& ctx, IR::Inst* inst) {
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}
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code.cvtsd2ss(result, result);
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if (ctx.FPSCR_DN()) {
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DefaultNaN<32>(code, result);
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ForceToDefaultNaN<32>(code, result);
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}
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ctx.reg_alloc.DefineValue(inst, result);
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