A64: Implement REV32 (vector)
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6b0010c940
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2 changed files with 32 additions and 1 deletions
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@ -612,7 +612,7 @@ INST(XTN, "XTN, XTN2", "0Q001
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//INST(URECPE, "URECPE", "0Q0011101z100001110010nnnnnddddd")
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//INST(FRECPE_3, "FRECPE", "0Q00111011111001110110nnnnnddddd")
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//INST(FRECPE_4, "FRECPE", "0Q0011101z100001110110nnnnnddddd")
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//INST(REV32_asimd, "REV32 (vector)", "0Q101110zz100000000010nnnnnddddd")
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INST(REV32_asimd, "REV32 (vector)", "0Q101110zz100000000010nnnnnddddd")
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//INST(UADDLP, "UADDLP", "0Q101110zz100000001010nnnnnddddd")
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//INST(USQADD_2, "USQADD", "0Q101110zz100000001110nnnnnddddd")
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//INST(CLZ_asimd, "CLZ (vector)", "0Q101110zz100000010010nnnnnddddd")
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@ -24,6 +24,37 @@ bool TranslatorVisitor::REV16_asimd(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
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return true;
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}
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bool TranslatorVisitor::REV32_asimd(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
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const u32 zext_size = size.ZeroExtend();
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if (zext_size > 1) {
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return UnallocatedEncoding();
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}
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const size_t datasize = Q ? 128 : 64;
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const size_t esize = 16 << zext_size;
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const u8 shift = static_cast<u8>(8 << zext_size);
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const IR::U128 data = V(datasize, Vn);
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// TODO: Consider factoring byte swapping code out into its own opcode.
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// Technically the rest of the following code can be a PSHUFB
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// in the presence of SSSE3.
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IR::U128 result = ir.VectorOr(ir.VectorLogicalShiftRight(esize, data, shift),
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ir.VectorLogicalShiftLeft(esize, data, shift));
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// If dealing with 8-bit elements we'll need to shuffle the bytes in each halfword
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// e.g. Assume the following numbers point out bytes in a 32-bit word, we're essentially
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// changing [3, 2, 1, 0] to [2, 3, 0, 1]
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if (zext_size == 0) {
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result = ir.VectorShuffleLowHalfwords(result, 0b10110001);
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result = ir.VectorShuffleHighHalfwords(result, 0b10110001);
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}
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V(datasize, Vd, result);
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return true;
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}
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bool TranslatorVisitor::UCVTF_int_2(bool sz, Vec Vn, Vec Vd) {
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const auto esize = sz ? 64 : 32;
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