A64: Implement REV32 (vector)

This commit is contained in:
Lioncash 2018-03-17 21:05:30 -04:00 committed by MerryMage
parent 6b0010c940
commit 9128988dc3
2 changed files with 32 additions and 1 deletions

View file

@ -612,7 +612,7 @@ INST(XTN, "XTN, XTN2", "0Q001
//INST(URECPE, "URECPE", "0Q0011101z100001110010nnnnnddddd")
//INST(FRECPE_3, "FRECPE", "0Q00111011111001110110nnnnnddddd")
//INST(FRECPE_4, "FRECPE", "0Q0011101z100001110110nnnnnddddd")
//INST(REV32_asimd, "REV32 (vector)", "0Q101110zz100000000010nnnnnddddd")
INST(REV32_asimd, "REV32 (vector)", "0Q101110zz100000000010nnnnnddddd")
//INST(UADDLP, "UADDLP", "0Q101110zz100000001010nnnnnddddd")
//INST(USQADD_2, "USQADD", "0Q101110zz100000001110nnnnnddddd")
//INST(CLZ_asimd, "CLZ (vector)", "0Q101110zz100000010010nnnnnddddd")

View file

@ -24,6 +24,37 @@ bool TranslatorVisitor::REV16_asimd(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
return true;
}
bool TranslatorVisitor::REV32_asimd(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
const u32 zext_size = size.ZeroExtend();
if (zext_size > 1) {
return UnallocatedEncoding();
}
const size_t datasize = Q ? 128 : 64;
const size_t esize = 16 << zext_size;
const u8 shift = static_cast<u8>(8 << zext_size);
const IR::U128 data = V(datasize, Vn);
// TODO: Consider factoring byte swapping code out into its own opcode.
// Technically the rest of the following code can be a PSHUFB
// in the presence of SSSE3.
IR::U128 result = ir.VectorOr(ir.VectorLogicalShiftRight(esize, data, shift),
ir.VectorLogicalShiftLeft(esize, data, shift));
// If dealing with 8-bit elements we'll need to shuffle the bytes in each halfword
// e.g. Assume the following numbers point out bytes in a 32-bit word, we're essentially
// changing [3, 2, 1, 0] to [2, 3, 0, 1]
if (zext_size == 0) {
result = ir.VectorShuffleLowHalfwords(result, 0b10110001);
result = ir.VectorShuffleHighHalfwords(result, 0b10110001);
}
V(datasize, Vd, result);
return true;
}
bool TranslatorVisitor::UCVTF_int_2(bool sz, Vec Vn, Vec Vd) {
const auto esize = sz ? 64 : 32;