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simd_scalar_two_register_misc: Implement FCVT{AS, AU, MS, MU, NS, NU, PS, PU, ZS, ZU} (vector)'s scalar double/single-precision variants

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We can simply implement this in terms of the fixed-point IR opcodes.
This commit is contained in:
Lioncash 2018-07-17 12:27:18 -04:00 committed by MerryMage
parent 5b39e8dcf8
commit 91abf87169
2 changed files with 80 additions and 10 deletions
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20
src/frontend/A64/decoder/a64.inc
View file

@ -359,11 +359,11 @@ INST(FACGT_2, "FACGT", "01111
// Data Processing - FP and SIMD - Scalar two register misc
//INST(FCVTNS_1, "FCVTNS (vector)", "0101111001111001101010nnnnnddddd")
//INST(FCVTNS_2, "FCVTNS (vector)", "010111100z100001101010nnnnnddddd")
INST(FCVTNS_2, "FCVTNS (vector)", "010111100z100001101010nnnnnddddd")
//INST(FCVTMS_1, "FCVTMS (vector)", "0101111001111001101110nnnnnddddd")
//INST(FCVTMS_2, "FCVTMS (vector)", "010111100z100001101110nnnnnddddd")
INST(FCVTMS_2, "FCVTMS (vector)", "010111100z100001101110nnnnnddddd")
//INST(FCVTAS_1, "FCVTAS (vector)", "0101111001111001110010nnnnnddddd")
//INST(FCVTAS_2, "FCVTAS (vector)", "010111100z100001110010nnnnnddddd")
INST(FCVTAS_2, "FCVTAS (vector)", "010111100z100001110010nnnnnddddd")
//INST(SCVTF_int_1, "SCVTF (vector, integer)", "0101111001111001110110nnnnnddddd")
INST(SCVTF_int_2, "SCVTF (vector, integer)", "010111100z100001110110nnnnnddddd")
//INST(FCMGT_zero_1, "FCMGT (zero)", "0101111011111000110010nnnnnddddd")
@ -373,19 +373,19 @@ INST(FCMEQ_zero_2, "FCMEQ (zero)", "01011
//INST(FCMLT_1, "FCMLT (zero)", "0101111011111000111010nnnnnddddd")
INST(FCMLT_2, "FCMLT (zero)", "010111101z100000111010nnnnnddddd")
//INST(FCVTPS_1, "FCVTPS (vector)", "0101111011111001101010nnnnnddddd")
//INST(FCVTPS_2, "FCVTPS (vector)", "010111101z100001101010nnnnnddddd")
INST(FCVTPS_2, "FCVTPS (vector)", "010111101z100001101010nnnnnddddd")
//INST(FCVTZS_int_1, "FCVTZS (vector, integer)", "0101111011111001101110nnnnnddddd")
//INST(FCVTZS_int_2, "FCVTZS (vector, integer)", "010111101z100001101110nnnnnddddd")
INST(FCVTZS_int_2, "FCVTZS (vector, integer)", "010111101z100001101110nnnnnddddd")
//INST(FRECPE_1, "FRECPE", "0101111011111001110110nnnnnddddd")
//INST(FRECPE_2, "FRECPE", "010111101z100001110110nnnnnddddd")
//INST(FRECPX_1, "FRECPX", "0101111011111001111110nnnnnddddd")
//INST(FRECPX_2, "FRECPX", "010111101z100001111110nnnnnddddd")
//INST(FCVTNU_1, "FCVTNU (vector)", "0111111001111001101010nnnnnddddd")
//INST(FCVTNU_2, "FCVTNU (vector)", "011111100z100001101010nnnnnddddd")
INST(FCVTNU_2, "FCVTNU (vector)", "011111100z100001101010nnnnnddddd")
//INST(FCVTMU_1, "FCVTMU (vector)", "0111111001111001101110nnnnnddddd")
//INST(FCVTMU_2, "FCVTMU (vector)", "011111100z100001101110nnnnnddddd")
INST(FCVTMU_2, "FCVTMU (vector)", "011111100z100001101110nnnnnddddd")
//INST(FCVTAU_1, "FCVTAU (vector)", "0111111001111001110010nnnnnddddd")
//INST(FCVTAU_2, "FCVTAU (vector)", "011111100z100001110010nnnnnddddd")
INST(FCVTAU_2, "FCVTAU (vector)", "011111100z100001110010nnnnnddddd")
//INST(UCVTF_int_1, "UCVTF (vector, integer)", "0111111001111001110110nnnnnddddd")
INST(UCVTF_int_2, "UCVTF (vector, integer)", "011111100z100001110110nnnnnddddd")
//INST(FCMGE_zero_1, "FCMGE (zero)", "0111111011111000110010nnnnnddddd")
@ -393,9 +393,9 @@ INST(FCMGE_zero_2, "FCMGE (zero)", "01111
//INST(FCMLE_1, "FCMLE (zero)", "0111111011111000110110nnnnnddddd")
INST(FCMLE_2, "FCMLE (zero)", "011111101z100000110110nnnnnddddd")
//INST(FCVTPU_1, "FCVTPU (vector)", "0111111011111001101010nnnnnddddd")
//INST(FCVTPU_2, "FCVTPU (vector)", "011111101z100001101010nnnnnddddd")
INST(FCVTPU_2, "FCVTPU (vector)", "011111101z100001101010nnnnnddddd")
//INST(FCVTZU_int_1, "FCVTZU (vector, integer)", "0111111011111001101110nnnnnddddd")
//INST(FCVTZU_int_2, "FCVTZU (vector, integer)", "011111101z100001101110nnnnnddddd")
INST(FCVTZU_int_2, "FCVTZU (vector, integer)", "011111101z100001101110nnnnnddddd")
//INST(FRSQRTE_1, "FRSQRTE", "0111111011111001110110nnnnnddddd")
//INST(FRSQRTE_2, "FRSQRTE", "011111101z100001110110nnnnnddddd")

70
src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp
View file

@ -16,6 +16,11 @@ enum class ComparisonType {
LT
};
enum class Signedness {
Signed,
Unsigned
};
bool ScalarFPCompareAgainstZero(TranslatorVisitor& v, bool sz, Vec Vn, Vec Vd, ComparisonType type) {
const size_t esize = sz ? 64 : 32;
const size_t datasize = esize;
@ -43,6 +48,31 @@ bool ScalarFPCompareAgainstZero(TranslatorVisitor& v, bool sz, Vec Vn, Vec Vd, C
v.V_scalar(datasize, Vd, v.ir.VectorGetElement(esize, result, 0));
return true;
}
bool ScalarFPConvertWithRound(TranslatorVisitor& v, bool sz, Vec Vn, Vec Vd,
FP::RoundingMode rmode, Signedness sign) {
const size_t esize = sz ? 64 : 32;
const IR::U32U64 operand = v.V_scalar(esize, Vn);
const IR::U32U64 result = [&]() -> IR::U32U64 {
if (sz) {
if (sign == Signedness::Signed) {
return v.ir.FPDoubleToFixedS64(operand, 0, rmode);
}
return v.ir.FPDoubleToFixedU64(operand, 0, rmode);
}
if (sign == Signedness::Signed) {
return v.ir.FPSingleToFixedS32(operand, 0, rmode);
}
return v.ir.FPSingleToFixedU32(operand, 0, rmode);
}();
v.V_scalar(esize, Vd, result);
return true;
}
} // Anonymous namespace
bool TranslatorVisitor::ABS_1(Imm<2> size, Vec Vn, Vec Vd) {
@ -78,6 +108,46 @@ bool TranslatorVisitor::FCMLT_2(bool sz, Vec Vn, Vec Vd) {
return ScalarFPCompareAgainstZero(*this, sz, Vn, Vd, ComparisonType::LT);
}
bool TranslatorVisitor::FCVTAS_2(bool sz, Vec Vn, Vec Vd) {
return ScalarFPConvertWithRound(*this, sz, Vn, Vd, FP::RoundingMode::ToNearest_TieAwayFromZero, Signedness::Signed);
}
bool TranslatorVisitor::FCVTAU_2(bool sz, Vec Vn, Vec Vd) {
return ScalarFPConvertWithRound(*this, sz, Vn, Vd, FP::RoundingMode::ToNearest_TieAwayFromZero, Signedness::Unsigned);
}
bool TranslatorVisitor::FCVTMS_2(bool sz, Vec Vn, Vec Vd) {
return ScalarFPConvertWithRound(*this, sz, Vn, Vd, FP::RoundingMode::TowardsMinusInfinity, Signedness::Signed);
}
bool TranslatorVisitor::FCVTMU_2(bool sz, Vec Vn, Vec Vd) {
return ScalarFPConvertWithRound(*this, sz, Vn, Vd, FP::RoundingMode::TowardsMinusInfinity, Signedness::Unsigned);
}
bool TranslatorVisitor::FCVTNS_2(bool sz, Vec Vn, Vec Vd) {
return ScalarFPConvertWithRound(*this, sz, Vn, Vd, FP::RoundingMode::ToNearest_TieEven, Signedness::Signed);
}
bool TranslatorVisitor::FCVTNU_2(bool sz, Vec Vn, Vec Vd) {
return ScalarFPConvertWithRound(*this, sz, Vn, Vd, FP::RoundingMode::ToNearest_TieEven, Signedness::Unsigned);
}
bool TranslatorVisitor::FCVTPS_2(bool sz, Vec Vn, Vec Vd) {
return ScalarFPConvertWithRound(*this, sz, Vn, Vd, FP::RoundingMode::TowardsPlusInfinity, Signedness::Signed);
}
bool TranslatorVisitor::FCVTPU_2(bool sz, Vec Vn, Vec Vd) {
return ScalarFPConvertWithRound(*this, sz, Vn, Vd, FP::RoundingMode::TowardsPlusInfinity, Signedness::Unsigned);
}
bool TranslatorVisitor::FCVTZS_int_2(bool sz, Vec Vn, Vec Vd) {
return ScalarFPConvertWithRound(*this, sz, Vn, Vd, FP::RoundingMode::TowardsZero, Signedness::Signed);
}
bool TranslatorVisitor::FCVTZU_int_2(bool sz, Vec Vn, Vec Vd) {
return ScalarFPConvertWithRound(*this, sz, Vn, Vd, FP::RoundingMode::TowardsZero, Signedness::Unsigned);
}
bool TranslatorVisitor::NEG_1(Imm<2> size, Vec Vn, Vec Vd) {
if (size != 0b11) {
return ReservedValue();