mirrors/dynarmic
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

thumb32: Implement SHADD16/UHADD16

Browse source
This commit is contained in:
Lioncash 2021-02-01 17:13:44 -05:00
parent aa49b0db89
commit 94f8efbb03
4 changed files with 35 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
src/frontend/A32/decoder/thumb32.h
View file

@ -247,7 +247,7 @@ std::optional<std::reference_wrapper<const Thumb32Matcher<V>>> DecodeThumb32(u32
INST(&V::thumb32_QSUB16, "QSUB16", "111110101101nnnn1111dddd0001mmmm"), INST(&V::thumb32_QSUB16, "QSUB16", "111110101101nnnn1111dddd0001mmmm"),
INST(&V::thumb32_QADD8, "QADD8", "111110101000nnnn1111dddd0001mmmm"), INST(&V::thumb32_QADD8, "QADD8", "111110101000nnnn1111dddd0001mmmm"),
INST(&V::thumb32_QSUB8, "QSUB8", "111110101100nnnn1111dddd0001mmmm"), INST(&V::thumb32_QSUB8, "QSUB8", "111110101100nnnn1111dddd0001mmmm"),
//INST(&V::thumb32_SHADD16, "SHADD16", "111110101001----1111----0010----"), INST(&V::thumb32_SHADD16, "SHADD16", "111110101001nnnn1111dddd0010mmmm"),
//INST(&V::thumb32_SHASX, "SHASX", "111110101010----1111----0010----"), //INST(&V::thumb32_SHASX, "SHASX", "111110101010----1111----0010----"),
//INST(&V::thumb32_SHSAX, "SHSAX", "111110101110----1111----0010----"), //INST(&V::thumb32_SHSAX, "SHSAX", "111110101110----1111----0010----"),
//INST(&V::thumb32_SHSUB16, "SHSUB16", "111110101101----1111----0010----"), //INST(&V::thumb32_SHSUB16, "SHSUB16", "111110101101----1111----0010----"),
@ -267,7 +267,7 @@ std::optional<std::reference_wrapper<const Thumb32Matcher<V>>> DecodeThumb32(u32
INST(&V::thumb32_UQSUB16, "UQSUB16", "111110101101nnnn1111dddd0101mmmm"), INST(&V::thumb32_UQSUB16, "UQSUB16", "111110101101nnnn1111dddd0101mmmm"),
INST(&V::thumb32_UQADD8, "UQADD8", "111110101000nnnn1111dddd0101mmmm"), INST(&V::thumb32_UQADD8, "UQADD8", "111110101000nnnn1111dddd0101mmmm"),
INST(&V::thumb32_UQSUB8, "UQSUB8", "111110101100nnnn1111dddd0101mmmm"), INST(&V::thumb32_UQSUB8, "UQSUB8", "111110101100nnnn1111dddd0101mmmm"),
//INST(&V::thumb32_UHADD16, "UHADD16", "111110101001----1111----0110----"), INST(&V::thumb32_UHADD16, "UHADD16", "111110101001nnnn1111dddd0110mmmm"),
//INST(&V::thumb32_UHASX, "UHASX", "111110101010----1111----0110----"), //INST(&V::thumb32_UHASX, "UHASX", "111110101010----1111----0110----"),
//INST(&V::thumb32_UHSAX, "UHSAX", "111110101110----1111----0110----"), //INST(&V::thumb32_UHSAX, "UHSAX", "111110101110----1111----0110----"),
//INST(&V::thumb32_UHSUB16, "UHSUB16", "111110101101----1111----0110----"), //INST(&V::thumb32_UHSUB16, "UHSUB16", "111110101101----1111----0110----"),

26
src/frontend/A32/translate/impl/thumb32_parallel.cpp
View file

@ -362,4 +362,30 @@ bool ThumbTranslatorVisitor::thumb32_UQSUB16(Reg n, Reg d, Reg m) {
return true; return true;
} }
bool ThumbTranslatorVisitor::thumb32_SHADD16(Reg n, Reg d, Reg m) {
if (d == Reg::PC || n == Reg::PC || m == Reg::PC) {
return UnpredictableInstruction();
}
const auto reg_m = ir.GetRegister(m);
const auto reg_n = ir.GetRegister(n);
const auto result = ir.PackedHalvingAddS16(reg_n, reg_m);
ir.SetRegister(d, result);
return true;
}
bool ThumbTranslatorVisitor::thumb32_UHADD16(Reg n, Reg d, Reg m) {
if (d == Reg::PC || n == Reg::PC || m == Reg::PC) {
return UnpredictableInstruction();
}
const auto reg_m = ir.GetRegister(m);
const auto reg_n = ir.GetRegister(n);
const auto result = ir.PackedHalvingAddU16(reg_n, reg_m);
ir.SetRegister(d, result);
return true;
}
} // namespace Dynarmic::A32 } // namespace Dynarmic::A32

3
src/frontend/A32/translate/impl/translate_thumb.h
View file

@ -154,6 +154,9 @@ struct ThumbTranslatorVisitor final {
bool thumb32_UQSAX(Reg n, Reg d, Reg m); bool thumb32_UQSAX(Reg n, Reg d, Reg m);
bool thumb32_UQSUB8(Reg n, Reg d, Reg m); bool thumb32_UQSUB8(Reg n, Reg d, Reg m);
bool thumb32_UQSUB16(Reg n, Reg d, Reg m); bool thumb32_UQSUB16(Reg n, Reg d, Reg m);
bool thumb32_SHADD16(Reg n, Reg d, Reg m);
bool thumb32_UHADD16(Reg n, Reg d, Reg m);
}; };
} // namespace Dynarmic::A32 } // namespace Dynarmic::A32

4
tests/A32/fuzz_thumb.cpp
View file

@ -432,6 +432,8 @@ TEST_CASE("Fuzz Thumb32 instructions set", "[JitX64][Thumb][Thumb32]") {
three_reg_not_r15), three_reg_not_r15),
ThumbInstGen("111110101010nnnn1111dddd1000mmmm", // SEL ThumbInstGen("111110101010nnnn1111dddd1000mmmm", // SEL
three_reg_not_r15), three_reg_not_r15),
ThumbInstGen("111110101001nnnn1111dddd0010mmmm", // SHADD16
three_reg_not_r15),
ThumbInstGen("111110101110nnnn1111dddd0000mmmm", // SSAX ThumbInstGen("111110101110nnnn1111dddd0000mmmm", // SSAX
three_reg_not_r15), three_reg_not_r15),
ThumbInstGen("111110101100nnnn1111dddd0000mmmm", // SSUB8 ThumbInstGen("111110101100nnnn1111dddd0000mmmm", // SSUB8
@ -444,6 +446,8 @@ TEST_CASE("Fuzz Thumb32 instructions set", "[JitX64][Thumb][Thumb32]") {
three_reg_not_r15), three_reg_not_r15),
ThumbInstGen("111110101010nnnn1111dddd0100mmmm", // UASX ThumbInstGen("111110101010nnnn1111dddd0100mmmm", // UASX
three_reg_not_r15), three_reg_not_r15),
ThumbInstGen("111110101001nnnn1111dddd0110mmmm", // UHADD16
three_reg_not_r15),
ThumbInstGen("111110101000nnnn1111dddd0101mmmm", // UQADD8 ThumbInstGen("111110101000nnnn1111dddd0101mmmm", // UQADD8
three_reg_not_r15), three_reg_not_r15),
ThumbInstGen("111110101001nnnn1111dddd0101mmmm", // UQADD16 ThumbInstGen("111110101001nnnn1111dddd0101mmmm", // UQADD16