frontend/ir_emitter: Add half-precision opcode variant of FPVectorRSqrtStepFused
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824c551ba2
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4 changed files with 45 additions and 35 deletions
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@ -1273,51 +1273,57 @@ static void EmitRSqrtStepFused(BlockOfCode& code, EmitContext& ctx, IR::Inst* in
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}
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};
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tFMA) && code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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if constexpr (fsize != 16) {
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tFMA) && code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm();
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const Xbyak::Xmm operand1 = ctx.reg_alloc.UseXmm(args[0]);
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const Xbyak::Xmm operand2 = ctx.reg_alloc.UseXmm(args[1]);
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const Xbyak::Xmm tmp = ctx.reg_alloc.ScratchXmm();
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const Xbyak::Xmm mask = ctx.reg_alloc.ScratchXmm();
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const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm();
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const Xbyak::Xmm operand1 = ctx.reg_alloc.UseXmm(args[0]);
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const Xbyak::Xmm operand2 = ctx.reg_alloc.UseXmm(args[1]);
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const Xbyak::Xmm tmp = ctx.reg_alloc.ScratchXmm();
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const Xbyak::Xmm mask = ctx.reg_alloc.ScratchXmm();
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Xbyak::Label end, fallback;
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Xbyak::Label end, fallback;
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code.vmovaps(result, GetVectorOf<fsize, false, 0, 3>(code));
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FCODE(vfnmadd231p)(result, operand1, operand2);
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code.vmovaps(result, GetVectorOf<fsize, false, 0, 3>(code));
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FCODE(vfnmadd231p)(result, operand1, operand2);
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// An explanation for this is given in EmitFPRSqrtStepFused.
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code.vmovaps(mask, GetVectorOf<fsize, fsize == 32 ? 0x7f000000 : 0x7fe0000000000000>(code));
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FCODE(vandp)(tmp, result, mask);
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if constexpr (fsize == 32) {
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code.vpcmpeqd(tmp, tmp, mask);
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} else {
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code.vpcmpeqq(tmp, tmp, mask);
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// An explanation for this is given in EmitFPRSqrtStepFused.
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code.vmovaps(mask, GetVectorOf<fsize, fsize == 32 ? 0x7f000000 : 0x7fe0000000000000>(code));
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FCODE(vandp)(tmp, result, mask);
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if constexpr (fsize == 32) {
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code.vpcmpeqd(tmp, tmp, mask);
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} else {
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code.vpcmpeqq(tmp, tmp, mask);
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}
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code.ptest(tmp, tmp);
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code.jnz(fallback, code.T_NEAR);
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FCODE(vmulp)(result, result, GetVectorOf<fsize, false, -1, 1>(code));
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code.L(end);
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code.SwitchToFarCode();
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code.L(fallback);
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code.sub(rsp, 8);
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ABI_PushCallerSaveRegistersAndAdjustStackExcept(code, HostLocXmmIdx(result.getIdx()));
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EmitThreeOpFallbackWithoutRegAlloc(code, ctx, result, operand1, operand2, fallback_fn);
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ABI_PopCallerSaveRegistersAndAdjustStackExcept(code, HostLocXmmIdx(result.getIdx()));
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code.add(rsp, 8);
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code.jmp(end, code.T_NEAR);
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code.SwitchToNearCode();
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ctx.reg_alloc.DefineValue(inst, result);
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return;
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}
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code.ptest(tmp, tmp);
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code.jnz(fallback, code.T_NEAR);
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FCODE(vmulp)(result, result, GetVectorOf<fsize, false, -1, 1>(code));
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code.L(end);
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code.SwitchToFarCode();
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code.L(fallback);
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code.sub(rsp, 8);
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ABI_PushCallerSaveRegistersAndAdjustStackExcept(code, HostLocXmmIdx(result.getIdx()));
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EmitThreeOpFallbackWithoutRegAlloc(code, ctx, result, operand1, operand2, fallback_fn);
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ABI_PopCallerSaveRegistersAndAdjustStackExcept(code, HostLocXmmIdx(result.getIdx()));
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code.add(rsp, 8);
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code.jmp(end, code.T_NEAR);
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code.SwitchToNearCode();
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ctx.reg_alloc.DefineValue(inst, result);
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return;
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}
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EmitThreeOpFallback(code, ctx, inst, fallback_fn);
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}
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void EmitX64::EmitFPVectorRSqrtStepFused16(EmitContext& ctx, IR::Inst* inst) {
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EmitRSqrtStepFused<16>(code, ctx, inst);
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}
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void EmitX64::EmitFPVectorRSqrtStepFused32(EmitContext& ctx, IR::Inst* inst) {
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EmitRSqrtStepFused<32>(code, ctx, inst);
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}
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@ -2344,6 +2344,8 @@ U128 IREmitter::FPVectorRSqrtEstimate(size_t esize, const U128& a) {
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U128 IREmitter::FPVectorRSqrtStepFused(size_t esize, const U128& a, const U128& b) {
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switch (esize) {
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case 16:
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return Inst<U128>(Opcode::FPVectorRSqrtStepFused16, a, b);
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case 32:
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return Inst<U128>(Opcode::FPVectorRSqrtStepFused32, a, b);
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case 64:
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@ -351,6 +351,7 @@ bool Inst::ReadsFromAndWritesToFPSRCumulativeExceptionBits() const {
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case Opcode::FPVectorRSqrtEstimate16:
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case Opcode::FPVectorRSqrtEstimate32:
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case Opcode::FPVectorRSqrtEstimate64:
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case Opcode::FPVectorRSqrtStepFused16:
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case Opcode::FPVectorRSqrtStepFused32:
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case Opcode::FPVectorRSqrtStepFused64:
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case Opcode::FPVectorSqrt32:
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@ -586,6 +586,7 @@ OPCODE(FPVectorRoundInt64, U128, U128
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OPCODE(FPVectorRSqrtEstimate16, U128, U128 )
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OPCODE(FPVectorRSqrtEstimate32, U128, U128 )
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OPCODE(FPVectorRSqrtEstimate64, U128, U128 )
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OPCODE(FPVectorRSqrtStepFused16, U128, U128, U128 )
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OPCODE(FPVectorRSqrtStepFused32, U128, U128, U128 )
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OPCODE(FPVectorRSqrtStepFused64, U128, U128, U128 )
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OPCODE(FPVectorSqrt32, U128, U128 )
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