mirrors/dynarmic
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

VFP: Implement VSUB

Browse source
This commit is contained in:
MerryMage 2016-08-07 01:41:25 +01:00
parent ce6b5f8210
commit 97b5fa173f
8 changed files with 81 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

42
src/backend_x64/emit_x64.cpp
View file

@ -1148,6 +1148,48 @@ void EmitX64::EmitFPAdd64(IR::Block& block, IR::Inst* inst) {
}
}
void EmitX64::EmitFPSub32(IR::Block& block, IR::Inst* inst) {
IR::Value a = inst->GetArg(0);
IR::Value b = inst->GetArg(1);
X64Reg result = reg_alloc.UseDefRegister(a, inst, any_xmm);
X64Reg operand = reg_alloc.UseRegister(b, any_xmm);
X64Reg gpr_scratch = reg_alloc.ScratchRegister(any_gpr);
if (block.location.FPSCR_FTZ()) {
DenormalsAreZero32(code, result, gpr_scratch);
DenormalsAreZero32(code, operand, gpr_scratch);
}
code->SUBSS(result, R(operand));
if (block.location.FPSCR_FTZ()) {
FlushToZero32(code, result, gpr_scratch);
}
if (block.location.FPSCR_DN()) {
DefaultNaN32(code, routines, result);
}
}
void EmitX64::EmitFPSub64(IR::Block& block, IR::Inst* inst) {
IR::Value a = inst->GetArg(0);
IR::Value b = inst->GetArg(1);
X64Reg result = reg_alloc.UseDefRegister(a, inst, any_xmm);
X64Reg operand = reg_alloc.UseRegister(b, any_xmm);
X64Reg gpr_scratch = reg_alloc.ScratchRegister(any_gpr);
if (block.location.FPSCR_FTZ()) {
DenormalsAreZero64(code, routines, result, gpr_scratch);
DenormalsAreZero64(code, routines, operand, gpr_scratch);
}
code->SUBSD(result, R(operand));
if (block.location.FPSCR_FTZ()) {
FlushToZero64(code, routines, result, gpr_scratch);
}
if (block.location.FPSCR_DN()) {
DefaultNaN64(code, routines, result);
}
}
void EmitX64::EmitReadMemory8(IR::Block&, IR::Inst* inst) {
reg_alloc.HostCall(inst, inst->GetArg(0));

2
src/frontend/decoder/vfp2.h
View file

@ -71,7 +71,7 @@ boost::optional<const VFP2Matcher<V>&> DecodeVFP2(u32 instruction) {
// VNMUL
// VMUL
INST(&V::vfp2_VADD, "VADD", "cccc11100D11nnnndddd101zN0M0mmmm"),
// VSUB
INST(&V::vfp2_VSUB, "VSUB", "cccc11100D11nnnndddd101zN1M0mmmm"),
// VDIV
// Floating-point other instructions

4
src/frontend/disassembler/disassembler_arm.cpp
View file

@ -564,6 +564,10 @@ public:
return Common::StringFromFormat("vadd%s.%s %s, %s, %s", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D).c_str(), FPRegStr(sz, Vn, N).c_str(), FPRegStr(sz, Vm, M).c_str());
}
std::string vfp2_VSUB(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) {
return Common::StringFromFormat("vsub%s.%s %s, %s, %s", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D).c_str(), FPRegStr(sz, Vn, N).c_str(), FPRegStr(sz, Vm, M).c_str());
}
std::string vfp2_VABS(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) {
return Common::StringFromFormat("vadd%s.%s %s, %s", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D).c_str(), FPRegStr(sz, Vm, M).c_str());
}

10
src/frontend/ir/ir_emitter.cpp
View file

@ -292,6 +292,16 @@ IR::Value IREmitter::FPAdd64(const IR::Value& a, const IR::Value& b, bool fpscr_
return Inst(IR::Opcode::FPAdd64, {a, b});
}
IR::Value IREmitter::FPSub32(const IR::Value& a, const IR::Value& b, bool fpscr_controlled) {
ASSERT(fpscr_controlled);
return Inst(IR::Opcode::FPSub32, {a, b});
}
IR::Value IREmitter::FPSub64(const IR::Value& a, const IR::Value& b, bool fpscr_controlled) {
ASSERT(fpscr_controlled);
return Inst(IR::Opcode::FPSub64, {a, b});
}
IR::Value IREmitter::ReadMemory8(const IR::Value& vaddr) {
return Inst(IR::Opcode::ReadMemory8, {vaddr});
}

2
src/frontend/ir/ir_emitter.h
View file

@ -96,6 +96,8 @@ public:
IR::Value FPAbs64(const IR::Value& a);
IR::Value FPAdd32(const IR::Value& a, const IR::Value& b, bool fpscr_controlled);
IR::Value FPAdd64(const IR::Value& a, const IR::Value& b, bool fpscr_controlled);
IR::Value FPSub32(const IR::Value& a, const IR::Value& b, bool fpscr_controlled);
IR::Value FPSub64(const IR::Value& a, const IR::Value& b, bool fpscr_controlled);
IR::Value ReadMemory8(const IR::Value& vaddr);
IR::Value ReadMemory16(const IR::Value& vaddr);

2
src/frontend/ir/opcodes.inc
View file

@ -64,6 +64,8 @@ OPCODE(FPAbs32, T::F32, T::F32
OPCODE(FPAbs64, T::F64, T::F64 )
OPCODE(FPAdd32, T::F32, T::F32, T::F32 )
OPCODE(FPAdd64, T::F64, T::F64, T::F64 )
OPCODE(FPSub32, T::F32, T::F32, T::F32 )
OPCODE(FPSub64, T::F64, T::F64, T::F64 )
// Memory access
OPCODE(ReadMemory8, T::U8, T::U32 )

1
src/frontend/translate/translate_arm/translate_arm.h
View file

@ -320,6 +320,7 @@ struct ArmTranslatorVisitor final {
// Floating-point three-register data processing instructions
bool vfp2_VADD(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm);
bool vfp2_VSUB(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm);
// Floating-point misc instructions
bool vfp2_VABS(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm);

19
src/frontend/translate/translate_arm/vfp2.cpp
View file

@ -36,6 +36,25 @@ bool ArmTranslatorVisitor::vfp2_VADD(Cond cond, bool D, size_t Vn, size_t Vd, bo
return true;
}
bool ArmTranslatorVisitor::vfp2_VSUB(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm) {
if (ir.current_location.FPSCR_Len() != 1 || ir.current_location.FPSCR_Stride() != 1)
return InterpretThisInstruction(); // TODO: Vectorised floating point instructions
ExtReg d = ToExtReg(sz, Vd, D);
ExtReg n = ToExtReg(sz, Vn, N);
ExtReg m = ToExtReg(sz, Vm, M);
// VSUB.{F32,F64} <{S,D}d>, <{S,D}n>, <{S,D}m>
if (ConditionPassed(cond)) {
auto a = ir.GetExtendedRegister(n);
auto b = ir.GetExtendedRegister(m);
auto result = sz
? ir.FPSub64(a, b, true)
: ir.FPSub32(a, b, true);
ir.SetExtendedRegister(d, result);
}
return true;
}
bool ArmTranslatorVisitor::vfp2_VABS(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm) {
if (ir.current_location.FPSCR_Len() != 1 || ir.current_location.FPSCR_Stride() != 1)
return InterpretThisInstruction(); // TODO: Vectorised floating point instructions