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emit_x64_floating_point: AVX implementation of ZeroIfNaN

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Wunkolo 2021-05-28 17:47:37 -07:00 committed by MerryMage
parent e9c5c01eda
commit 9a23c09c3b
2 changed files with 15 additions and 13 deletions
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3
src/dynarmic/backend/x64/constants.h
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@ -64,8 +64,7 @@ enum class FpFixup : u8 {
}; };
// Generates 32-bit LUT for vfixupimm instruction // Generates 32-bit LUT for vfixupimm instruction
constexpr u32 FixupLUT( constexpr u32 FixupLUT(FpFixup src_qnan = FpFixup::A,
FpFixup src_qnan = FpFixup::A,
FpFixup src_snan = FpFixup::A, FpFixup src_snan = FpFixup::A,
FpFixup src_zero = FpFixup::A, FpFixup src_zero = FpFixup::A,
FpFixup src_posone = FpFixup::A, FpFixup src_posone = FpFixup::A,

7
src/dynarmic/backend/x64/emit_x64_floating_point.cpp
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@ -121,11 +121,14 @@ void ZeroIfNaN(BlockOfCode& code, Xbyak::Xmm xmm_value, Xbyak::Xmm xmm_scratch)
constexpr u32 nan_to_zero = FixupLUT(FpFixup::PosZero, constexpr u32 nan_to_zero = FixupLUT(FpFixup::PosZero,
FpFixup::PosZero); FpFixup::PosZero);
FCODE(vfixupimms)(xmm_value, xmm_value, code.MConst(ptr, u64(nan_to_zero)), u8(0)); FCODE(vfixupimms)(xmm_value, xmm_value, code.MConst(ptr, u64(nan_to_zero)), u8(0));
return; } else if (code.HasHostFeature(HostFeature::AVX)) {
} FCODE(vcmpords)(xmm_scratch, xmm_value, xmm_value);
FCODE(vandp)(xmm_value, xmm_value, xmm_scratch);
} else {
code.xorps(xmm_scratch, xmm_scratch); code.xorps(xmm_scratch, xmm_scratch);
FCODE(cmpords)(xmm_scratch, xmm_value); // true mask when ordered (i.e.: when not an NaN) FCODE(cmpords)(xmm_scratch, xmm_value); // true mask when ordered (i.e.: when not an NaN)
code.pand(xmm_value, xmm_scratch); code.pand(xmm_value, xmm_scratch);
}
} }
template<size_t fsize> template<size_t fsize>