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thumb32: Implement ADD/SUB (imm 2)

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This commit is contained in:
Lioncash 2021-02-25 09:46:19 -05:00
parent 68885fdb3c
commit 9d5505422f
3 changed files with 30 additions and 2 deletions
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4
src/frontend/A32/decoder/thumb32.inc
View file

@ -72,10 +72,10 @@ INST(thumb32_EOR_imm, "EOR (imm)", "11110v00100Snnnn0vvvdd
// Data Processing (Plain Binary Immediate) // Data Processing (Plain Binary Immediate)
//INST(thumb32_ADR, "ADR", "11110-10000011110---------------") //INST(thumb32_ADR, "ADR", "11110-10000011110---------------")
//INST(thumb32_ADD_imm_2, "ADD (imm)", "11110-100000----0---------------") INST(thumb32_ADD_imm_2, "ADD (imm)", "11110i10000011010iiiddddiiiiiiii")
INST(thumb32_MOVW_imm, "MOVW (imm)", "11110i100100iiii0iiiddddiiiiiiii") INST(thumb32_MOVW_imm, "MOVW (imm)", "11110i100100iiii0iiiddddiiiiiiii")
//INST(thumb32_ADR, "ADR", "11110-10101011110---------------") //INST(thumb32_ADR, "ADR", "11110-10101011110---------------")
//INST(thumb32_SUB_imm_2, "SUB (imm)", "11110-101010----0---------------") INST(thumb32_SUB_imm_2, "SUB (imm)", "11110i10101011010iiiddddiiiiiiii")
INST(thumb32_MOVT, "MOVT", "11110i101100iiii0iiiddddiiiiiiii") INST(thumb32_MOVT, "MOVT", "11110i101100iiii0iiiddddiiiiiiii")
//INST(thumb32_SSAT, "SSAT", "11110-110000----0---------------") //INST(thumb32_SSAT, "SSAT", "11110-110000----0---------------")
//INST(thumb32_SSAT, "SSAT", "11110-110010----0---------------") //INST(thumb32_SSAT, "SSAT", "11110-110010----0---------------")

26
src/frontend/A32/translate/impl/thumb32_data_processing_plain_binary_immediate.cpp
View file

@ -35,6 +35,19 @@ static bool Saturation16(ThumbTranslatorVisitor& v, Reg n, Reg d, size_t saturat
return true; return true;
} }
bool ThumbTranslatorVisitor::thumb32_ADD_imm_2(Imm<1> imm1, Imm<3> imm3, Reg d, Imm<8> imm8) {
if (d == Reg::PC) {
return UnpredictableInstruction();
}
const u32 imm = concatenate(imm1, imm3, imm8).ZeroExtend();
const auto sp = ir.GetRegister(Reg::SP);
const auto result = ir.AddWithCarry(sp, ir.Imm32(imm), ir.Imm1(0));
ir.SetRegister(d, result.result);
return true;
}
bool ThumbTranslatorVisitor::thumb32_BFC(Imm<3> imm3, Reg d, Imm<2> imm2, Imm<5> msb) { bool ThumbTranslatorVisitor::thumb32_BFC(Imm<3> imm3, Reg d, Imm<2> imm2, Imm<5> msb) {
if (d == Reg::PC) { if (d == Reg::PC) {
return UnpredictableInstruction(); return UnpredictableInstruction();
@ -129,6 +142,19 @@ bool ThumbTranslatorVisitor::thumb32_SSAT16(Reg n, Reg d, Imm<4> sat_imm) {
return Saturation16(*this, n, d, sat_imm.ZeroExtend() + 1, &IREmitter::SignedSaturation); return Saturation16(*this, n, d, sat_imm.ZeroExtend() + 1, &IREmitter::SignedSaturation);
} }
bool ThumbTranslatorVisitor::thumb32_SUB_imm_2(Imm<1> imm1, Imm<3> imm3, Reg d, Imm<8> imm8) {
if (d == Reg::PC) {
return UnpredictableInstruction();
}
const u32 imm = concatenate(imm1, imm3, imm8).ZeroExtend();
const auto sp = ir.GetRegister(Reg::SP);
const auto result = ir.SubWithCarry(sp, ir.Imm32(imm), ir.Imm1(1));
ir.SetRegister(d, result.result);
return true;
}
bool ThumbTranslatorVisitor::thumb32_UBFX(Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, Imm<5> widthm1) { bool ThumbTranslatorVisitor::thumb32_UBFX(Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, Imm<5> widthm1) {
if (d == Reg::PC || n == Reg::PC) { if (d == Reg::PC || n == Reg::PC) {
return UnpredictableInstruction(); return UnpredictableInstruction();

2
src/frontend/A32/translate/impl/translate_thumb.h
View file

@ -160,12 +160,14 @@ struct ThumbTranslatorVisitor final {
bool thumb32_EOR_imm(Imm<1> i, bool S, Reg n, Imm<3> imm3, Reg d, Imm<8> imm8); bool thumb32_EOR_imm(Imm<1> i, bool S, Reg n, Imm<3> imm3, Reg d, Imm<8> imm8);
// thumb32 data processing (plain binary immediate) instructions. // thumb32 data processing (plain binary immediate) instructions.
bool thumb32_ADD_imm_2(Imm<1> imm1, Imm<3> imm3, Reg d, Imm<8> imm8);
bool thumb32_BFC(Imm<3> imm3, Reg d, Imm<2> imm2, Imm<5> msb); bool thumb32_BFC(Imm<3> imm3, Reg d, Imm<2> imm2, Imm<5> msb);
bool thumb32_BFI(Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, Imm<5> msb); bool thumb32_BFI(Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, Imm<5> msb);
bool thumb32_MOVT(Imm<1> imm1, Imm<4> imm4, Imm<3> imm3, Reg d, Imm<8> imm8); bool thumb32_MOVT(Imm<1> imm1, Imm<4> imm4, Imm<3> imm3, Reg d, Imm<8> imm8);
bool thumb32_MOVW_imm(Imm<1> imm1, Imm<4> imm4, Imm<3> imm3, Reg d, Imm<8> imm8); bool thumb32_MOVW_imm(Imm<1> imm1, Imm<4> imm4, Imm<3> imm3, Reg d, Imm<8> imm8);
bool thumb32_SBFX(Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, Imm<5> widthm1); bool thumb32_SBFX(Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, Imm<5> widthm1);
bool thumb32_SSAT16(Reg n, Reg d, Imm<4> sat_imm); bool thumb32_SSAT16(Reg n, Reg d, Imm<4> sat_imm);
bool thumb32_SUB_imm_2(Imm<1> imm1, Imm<3> imm3, Reg d, Imm<8> imm8);
bool thumb32_UBFX(Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, Imm<5> widthm1); bool thumb32_UBFX(Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, Imm<5> widthm1);
bool thumb32_USAT16(Reg n, Reg d, Imm<4> sat_imm); bool thumb32_USAT16(Reg n, Reg d, Imm<4> sat_imm);