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A64: Implement DUP (element), scalar variant

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This commit is contained in:
MerryMage 2018-02-18 18:58:01 +00:00
parent 6541ec064d
commit 9df3793af0
2 changed files with 16 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -334,7 +334,7 @@ INST(AESIMC, "AESIMC", "01001
//INST(SHA256SU0, "SHA256SU0", "0101111000101000001010nnnnnddddd")
// Data Processing - FP and SIMD - Scalar copy
//INST(DUP_elt_1, "DUP (element)", "01011110000iiiii000001nnnnnddddd")
INST(DUP_elt_1, "DUP (element)", "01011110000iiiii000001nnnnnddddd")
// Data Processing - FP and SIMD - Scalar three
//INST(FMULX_vec_1, "FMULX", "01011110010mmmmm000111nnnnnddddd")

15
src/frontend/A64/translate/impl/simd_copy.cpp
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@ -9,6 +9,21 @@
namespace Dynarmic::A64 {
bool TranslatorVisitor::DUP_elt_1(Imm<5> imm5, Vec Vn, Vec Vd) {
const size_t size = Common::LowestSetBit(imm5.ZeroExtend());
if (size > 3) return UnallocatedEncoding();
const size_t index = imm5.ZeroExtend<size_t>() >> (size + 1);
const size_t idxdsize = imm5.Bit<4>() ? 128 : 64;
const size_t esize = 8 << size;
const IR::U128 operand = V(idxdsize, Vn);
const IR::UAny element = ir.VectorGetElement(esize, operand, index);
const IR::U128 result = ir.ZeroExtendToQuad(element);
V(128, Vd, result);
return true;
}
bool TranslatorVisitor::DUP_elt_2(bool Q, Imm<5> imm5, Vec Vn, Vec Vd) {
const size_t size = Common::LowestSetBit(imm5.ZeroExtend());
if (size > 3) return UnallocatedEncoding();