mirrors/dynarmic
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

A64: Implement UQADD/UQSUB's scalar variants

Browse source
This commit is contained in:
Lioncash 2018-08-13 14:25:57 -04:00 committed by MerryMage
parent acbaf04fef
commit a4b0e2ace6
2 changed files with 24 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
src/frontend/A64/decoder/a64.inc
View file

@ -455,8 +455,8 @@ INST(SSHL_1, "SSHL", "01011
INST(ADD_1, "ADD (vector)", "01011110zz1mmmmm100001nnnnnddddd") INST(ADD_1, "ADD (vector)", "01011110zz1mmmmm100001nnnnnddddd")
INST(CMTST_1, "CMTST", "01011110zz1mmmmm100011nnnnnddddd") INST(CMTST_1, "CMTST", "01011110zz1mmmmm100011nnnnnddddd")
//INST(SQDMULH_vec_1, "SQDMULH (vector)", "01011110zz1mmmmm101101nnnnnddddd") //INST(SQDMULH_vec_1, "SQDMULH (vector)", "01011110zz1mmmmm101101nnnnnddddd")
//INST(UQADD_1, "UQADD", "01111110zz1mmmmm000011nnnnnddddd") INST(UQADD_1, "UQADD", "01111110zz1mmmmm000011nnnnnddddd")
//INST(UQSUB_1, "UQSUB", "01111110zz1mmmmm001011nnnnnddddd") INST(UQSUB_1, "UQSUB", "01111110zz1mmmmm001011nnnnnddddd")
INST(CMHI_1, "CMHI (register)", "01111110zz1mmmmm001101nnnnnddddd") INST(CMHI_1, "CMHI (register)", "01111110zz1mmmmm001101nnnnnddddd")
INST(CMHS_1, "CMHS (register)", "01111110zz1mmmmm001111nnnnnddddd") INST(CMHS_1, "CMHS (register)", "01111110zz1mmmmm001111nnnnnddddd")
INST(USHL_1, "USHL", "01111110zz1mmmmm010001nnnnnddddd") INST(USHL_1, "USHL", "01111110zz1mmmmm010001nnnnnddddd")

22
src/frontend/A64/translate/impl/simd_scalar_three_same.cpp
View file

@ -124,6 +124,28 @@ bool TranslatorVisitor::SQSUB_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
return true; return true;
} }
bool TranslatorVisitor::UQADD_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
const size_t esize = 8 << size.ZeroExtend();
const IR::UAny operand1 = V_scalar(esize, Vn);
const IR::UAny operand2 = V_scalar(esize, Vm);
const auto result = ir.UnsignedSaturatedAdd(operand1, operand2);
ir.OrQC(result.overflow);
V_scalar(esize, Vd, result.result);
return true;
}
bool TranslatorVisitor::UQSUB_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
const size_t esize = 8 << size.ZeroExtend();
const IR::UAny operand1 = V_scalar(esize, Vn);
const IR::UAny operand2 = V_scalar(esize, Vm);
const auto result = ir.UnsignedSaturatedSub(operand1, operand2);
ir.OrQC(result.overflow);
V_scalar(esize, Vd, result.result);
return true;
}
bool TranslatorVisitor::ADD_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { bool TranslatorVisitor::ADD_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
if (size != 0b11) { if (size != 0b11) {
return ReservedValue(); return ReservedValue();