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translate_arm/reversal: Invert conditionals where applicable

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Lioncash 2019-03-01 01:51:47 -05:00 committed by MerryMage
parent 7be56e6b67
commit a72813599a
1 changed files with 31 additions and 20 deletions
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51
src/frontend/A32/translate/translate_arm/reversal.cpp
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@ -8,41 +8,52 @@
namespace Dynarmic::A32 { namespace Dynarmic::A32 {
// REV<c> <Rd>, <Rm>
bool ArmTranslatorVisitor::arm_REV(Cond cond, Reg d, Reg m) { bool ArmTranslatorVisitor::arm_REV(Cond cond, Reg d, Reg m) {
// REV<c> <Rd>, <Rm> if (d == Reg::PC || m == Reg::PC) {
if (d == Reg::PC || m == Reg::PC)
return UnpredictableInstruction(); return UnpredictableInstruction();
if (ConditionPassed(cond)) {
auto result = ir.ByteReverseWord(ir.GetRegister(m));
ir.SetRegister(d, result);
} }
if (!ConditionPassed(cond)) {
return true;
}
const auto result = ir.ByteReverseWord(ir.GetRegister(m));
ir.SetRegister(d, result);
return true; return true;
} }
// REV16<c> <Rd>, <Rm>
bool ArmTranslatorVisitor::arm_REV16(Cond cond, Reg d, Reg m) { bool ArmTranslatorVisitor::arm_REV16(Cond cond, Reg d, Reg m) {
if (d == Reg::PC || m == Reg::PC) if (d == Reg::PC || m == Reg::PC) {
return UnpredictableInstruction(); return UnpredictableInstruction();
if (ConditionPassed(cond)) {
auto reg_m = ir.GetRegister(m);
auto lo = ir.And(ir.LogicalShiftRight(reg_m, ir.Imm8(8), ir.Imm1(0)).result, ir.Imm32(0x00FF00FF));
auto hi = ir.And(ir.LogicalShiftLeft(reg_m, ir.Imm8(8), ir.Imm1(0)).result, ir.Imm32(0xFF00FF00));
auto result = ir.Or(lo, hi);
ir.SetRegister(d, result);
} }
if (!ConditionPassed(cond)) {
return true;
}
const auto reg_m = ir.GetRegister(m);
const auto lo = ir.And(ir.LogicalShiftRight(reg_m, ir.Imm8(8), ir.Imm1(0)).result, ir.Imm32(0x00FF00FF));
const auto hi = ir.And(ir.LogicalShiftLeft(reg_m, ir.Imm8(8), ir.Imm1(0)).result, ir.Imm32(0xFF00FF00));
const auto result = ir.Or(lo, hi);
ir.SetRegister(d, result);
return true; return true;
} }
// REVSH<c> <Rd>, <Rm>
bool ArmTranslatorVisitor::arm_REVSH(Cond cond, Reg d, Reg m) { bool ArmTranslatorVisitor::arm_REVSH(Cond cond, Reg d, Reg m) {
// REVSH<c> <Rd>, <Rm> if (d == Reg::PC || m == Reg::PC) {
if (d == Reg::PC || m == Reg::PC)
return UnpredictableInstruction(); return UnpredictableInstruction();
if (ConditionPassed(cond)) {
auto rev_half = ir.ByteReverseHalf(ir.LeastSignificantHalf(ir.GetRegister(m)));
ir.SetRegister(d, ir.SignExtendHalfToWord(rev_half));
} }
if (!ConditionPassed(cond)) {
return true;
}
const auto rev_half = ir.ByteReverseHalf(ir.LeastSignificantHalf(ir.GetRegister(m)));
ir.SetRegister(d, ir.SignExtendHalfToWord(rev_half));
return true; return true;
} }