thumb32: Implement STRD
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258ca93c53
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a74843ca17
3 changed files with 40 additions and 2 deletions
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@ -13,8 +13,8 @@ INST(thumb32_LDMDB, "LDMDB/LDMEA", "1110100100W1nnnniiiiii
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// Load/Store Dual, Load/Store Exclusive, Table Branch
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//INST(thumb32_STREX, "STREX", "111010000100--------------------")
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//INST(thumb32_LDREX, "LDREX", "111010000101--------------------")
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//INST(thumb32_STRD_imm_1, "STRD (imm)", "11101000-110--------------------")
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//INST(thumb32_STRD_imm_2, "STRD (imm)", "11101001-1-0--------------------")
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INST(thumb32_STRD_imm_1, "STRD (imm)", "11101000U110nnnnttttssssiiiiiiii")
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INST(thumb32_STRD_imm_2, "STRD (imm)", "11101001U1W0nnnnttttssssiiiiiiii")
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//INST(thumb32_LDRD_imm_1, "LDRD (lit)", "11101000-1111111----------------")
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//INST(thumb32_LDRD_imm_2, "LDRD (lit)", "11101001-1-11111----------------")
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//INST(thumb32_LDRD_imm_1, "LDRD (imm)", "11101000-111--------------------")
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@ -39,6 +39,42 @@ static bool TableBranch(ThumbTranslatorVisitor& v, Reg n, Reg m, bool half) {
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return false;
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}
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static bool StoreDual(ThumbTranslatorVisitor& v, bool P, bool U, bool W, Reg n, Reg t, Reg t2, Imm<8> imm8) {
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if (W && (n == t || n == t2)) {
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return v.UnpredictableInstruction();
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}
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if (n == Reg::PC || t == Reg::PC || t2 == Reg::PC) {
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return v.UnpredictableInstruction();
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}
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const u32 imm = imm8.ZeroExtend() << 2;
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const IR::U32 reg_n = v.ir.GetRegister(n);
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const IR::U32 reg_t = v.ir.GetRegister(t);
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const IR::U32 reg_t2 = v.ir.GetRegister(t2);
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const IR::U32 offset_address = U ? v.ir.Add(reg_n, v.ir.Imm32(imm))
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: v.ir.Sub(reg_n, v.ir.Imm32(imm));
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const IR::U32 address_1 = P ? offset_address
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: reg_n;
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const IR::U32 address_2 = v.ir.Add(address_1, v.ir.Imm32(4));
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v.ir.WriteMemory32(address_1, reg_t);
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v.ir.WriteMemory32(address_2, reg_t2);
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if (W) {
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v.ir.SetRegister(n, offset_address);
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}
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_STRD_imm_1(bool U, Reg n, Reg t, Reg t2, Imm<8> imm8) {
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return StoreDual(*this, false, U, true, n, t, t2, imm8);
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}
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bool ThumbTranslatorVisitor::thumb32_STRD_imm_2(bool U, bool W, Reg n, Reg t, Reg t2, Imm<8> imm8) {
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return StoreDual(*this, true, U, W, n, t, t2, imm8);
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}
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bool ThumbTranslatorVisitor::thumb32_TBB(Reg n, Reg m) {
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return TableBranch(*this, n, m, false);
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}
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@ -180,6 +180,8 @@ struct ThumbTranslatorVisitor final {
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bool thumb32_STMDB(bool W, Reg n, Imm<15> reg_list);
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// thumb32 load/store dual, load/store exclusive, table branch instructions
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bool thumb32_STRD_imm_1(bool U, Reg n, Reg t, Reg t2, Imm<8> imm8);
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bool thumb32_STRD_imm_2(bool U, bool W, Reg n, Reg t, Reg t2, Imm<8> imm8);
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bool thumb32_TBB(Reg n, Reg m);
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bool thumb32_TBH(Reg n, Reg m);
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