emit_x64_vector_saturation: Reduce esize noise in EmitVectorSignedSaturated
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1 changed files with 26 additions and 46 deletions
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@ -10,6 +10,24 @@
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#include "dynarmic/ir/microinstruction.h"
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#include "dynarmic/ir/opcodes.h"
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#define FCODE(NAME) \
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[&code](auto... args) { \
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if constexpr (esize == 32) { \
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code.NAME##s(args...); \
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} else { \
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code.NAME##d(args...); \
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} \
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}
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#define ICODE(NAME) \
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[&code](auto... args) { \
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if constexpr (esize == 32) { \
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code.NAME##d(args...); \
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} else { \
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code.NAME##q(args...); \
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} \
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}
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namespace Dynarmic::Backend::X64 {
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using namespace Xbyak::util;
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@ -65,43 +83,23 @@ void EmitVectorSignedSaturated(BlockOfCode& code, EmitContext& ctx, IR::Inst* in
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code.movaps(tmp, result);
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if (code.HasHostFeature(HostFeature::AVX512_Ortho | HostFeature::AVX512DQ)) {
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// Do a regular unsigned operation
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if constexpr (op == Op::Add) {
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if constexpr (esize == 32) {
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code.vpaddd(result, result, arg);
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} else {
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code.vpaddq(result, result, arg);
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}
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} else {
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if constexpr (esize == 32) {
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code.vpsubd(result, result, arg);
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} else {
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code.vpsubq(result, result, arg);
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}
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}
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// Determine if an overflow/underflow happened
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if constexpr (op == Op::Add) {
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ICODE(vpadd)(result, result, arg);
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code.vpternlogd(tmp, result, arg, 0b00100100);
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} else {
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ICODE(vpsub)(result, result, arg);
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code.vpternlogd(tmp, result, arg, 0b00011000);
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}
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// Masked write
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if constexpr (esize == 32) {
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code.vpmovd2m(k1, tmp);
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code.vpsrad(result | k1, result, 31);
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code.vpxord(result | k1, result, code.MConst(xword_b, msb_mask, msb_mask));
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} else {
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code.vpmovq2m(k1, tmp);
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code.vpsraq(result | k1, result, 63);
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code.vpxorq(result | k1, result, code.MConst(xword_b, msb_mask, msb_mask));
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}
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ICODE(vpsra)(result | k1, result, u8(esize - 1));
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ICODE(vpxor)(result | k1, result, code.MConst(xword_b, msb_mask, msb_mask));
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// Set ZF if an overflow happened
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code.ktestb(k1, k1);
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// Write Q if overflow/underflow occured
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code.setnz(overflow);
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code.or_(code.byte[code.r15 + code.GetJitStateInfo().offsetof_fpsr_qc], overflow);
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@ -109,22 +107,12 @@ void EmitVectorSignedSaturated(BlockOfCode& code, EmitContext& ctx, IR::Inst* in
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return;
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}
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// TODO AVX2 implementation
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code.movaps(xmm0, result);
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if constexpr (op == Op::Add) {
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if constexpr (esize == 32) {
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code.paddd(result, arg);
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ICODE(padd)(result, arg);
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} else {
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code.paddq(result, arg);
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}
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} else {
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if constexpr (esize == 32) {
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code.psubd(result, arg);
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} else {
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code.psubq(result, arg);
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}
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ICODE(psub)(result, arg);
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}
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code.pxor(tmp, result);
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@ -145,22 +133,14 @@ void EmitVectorSignedSaturated(BlockOfCode& code, EmitContext& ctx, IR::Inst* in
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if (code.HasHostFeature(HostFeature::SSE41)) {
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code.ptest(xmm0, code.MConst(xword, msb_mask, msb_mask));
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} else {
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if constexpr (esize == 32) {
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code.movmskps(overflow.cvt32(), xmm0);
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} else {
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code.movmskpd(overflow.cvt32(), xmm0);
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}
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FCODE(movmskp)(overflow.cvt32(), xmm0);
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code.test(overflow.cvt32(), overflow.cvt32());
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}
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code.setnz(overflow);
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code.or_(code.byte[code.r15 + code.GetJitStateInfo().offsetof_fpsr_qc], overflow);
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if (code.HasHostFeature(HostFeature::SSE41)) {
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if constexpr (esize == 32) {
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code.blendvps(result, tmp);
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} else {
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code.blendvpd(result, tmp);
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}
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FCODE(blendvp)(result, tmp);
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ctx.reg_alloc.DefineValue(inst, result);
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} else {
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