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X86_Backend: set fences correctly for memory barriers and synchronization.

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Fernando Sahmkow 2022-02-01 14:32:11 +01:00 committed by merry
parent 0cafcc1af9
commit a8cbfd9af4
2 changed files with 4 additions and 2 deletions
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3
src/dynarmic/backend/x64/a32_emit_x64.cpp
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@ -715,10 +715,11 @@ void A32EmitX64::EmitA32SetGEFlagsCompressed(A32EmitContext& ctx, IR::Inst* inst
void A32EmitX64::EmitA32DataSynchronizationBarrier(A32EmitContext&, IR::Inst*) { void A32EmitX64::EmitA32DataSynchronizationBarrier(A32EmitContext&, IR::Inst*) {
code.mfence(); code.mfence();
code.lfence();
} }
void A32EmitX64::EmitA32DataMemoryBarrier(A32EmitContext&, IR::Inst*) { void A32EmitX64::EmitA32DataMemoryBarrier(A32EmitContext&, IR::Inst*) {
code.lfence(); code.mfence();
} }
void A32EmitX64::EmitA32InstructionSynchronizationBarrier(A32EmitContext& ctx, IR::Inst*) { void A32EmitX64::EmitA32InstructionSynchronizationBarrier(A32EmitContext& ctx, IR::Inst*) {

3
src/dynarmic/backend/x64/a64_emit_x64.cpp
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@ -668,10 +668,11 @@ void A64EmitX64::EmitA64InstructionCacheOperationRaised(A64EmitContext& ctx, IR:
void A64EmitX64::EmitA64DataSynchronizationBarrier(A64EmitContext&, IR::Inst*) { void A64EmitX64::EmitA64DataSynchronizationBarrier(A64EmitContext&, IR::Inst*) {
code.mfence(); code.mfence();
code.lfence();
} }
void A64EmitX64::EmitA64DataMemoryBarrier(A64EmitContext&, IR::Inst*) { void A64EmitX64::EmitA64DataMemoryBarrier(A64EmitContext&, IR::Inst*) {
code.lfence(); code.mfence();
} }
void A64EmitX64::EmitA64InstructionSynchronizationBarrier(A64EmitContext& ctx, IR::Inst*) { void A64EmitX64::EmitA64InstructionSynchronizationBarrier(A64EmitContext& ctx, IR::Inst*) {