Implement thumb1_CMP_imm
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98f300144b
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aa72323823
4 changed files with 17 additions and 2 deletions
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@ -451,6 +451,7 @@ void EmitX64::EmitSubWithCarry(IR::Value* value_) {
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: X64Reg::INVALID_REG;
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// TODO: Consider using LEA.
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// TODO: Optimize case when result isn't used but flags are (use a CMP instruction instead).
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// Note that x64 CF is inverse of what the ARM carry flag is here.
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code->BT(32, R(carry), Imm8(0));
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@ -56,7 +56,7 @@ private:
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};
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template <typename V>
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static const std::array<Thumb1Matcher<V>, 15> g_thumb1_instruction_table {{
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static const std::array<Thumb1Matcher<V>, 16> g_thumb1_instruction_table {{
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#define INST(fn, name, bitstring) detail::detail<Thumb1Matcher, u16, 16>::GetMatcher<decltype(fn), fn>(name, bitstring)
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@ -69,7 +69,7 @@ static const std::array<Thumb1Matcher<V>, 15> g_thumb1_instruction_table {{
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{ INST(&V::thumb1_ADD_imm, "ADD (imm)", "0001110vvvnnnddd") },
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{ INST(&V::thumb1_SUB_imm, "SUB (imm)", "0001111vvvnnnddd") },
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{ INST(&V::thumb1_MOV_imm, "MOV (imm)", "00100dddvvvvvvvv") },
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//{ INST(&V::thumb1_CMP_ri, "CMP (ri)", "00101dddvvvvvvvv") },
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{ INST(&V::thumb1_CMP_imm, "CMP (imm)", "00101nnnvvvvvvvv") },
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//{ INST(&V::thumb1_ADD_ri, "ADD (ri)", "00110dddvvvvvvvv") },
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//{ INST(&V::thumb1_SUB_ri, "SUB (ri)", "00111dddvvvvvvvv") },
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@ -134,6 +134,10 @@ public:
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return Common::StringFromFormat("movs %s, #%u", RegStr(d), imm8);
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}
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std::string thumb1_CMP_imm(Reg n, Imm8 imm8) {
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return Common::StringFromFormat("cmp %s, #%u", RegStr(n), imm8);
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}
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std::string thumb1_AND_reg(Reg m, Reg d_n) {
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return Common::StringFromFormat("ands %s, %s", RegStr(d_n), RegStr(m));
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}
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@ -120,6 +120,16 @@ struct TranslatorVisitor final {
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ir.SetZFlag(ir.IsZero(result));
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return true;
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}
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bool thumb1_CMP_imm(Reg n, Imm8 imm8) {
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u32 imm32 = imm8 & 0xFF;
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// CMP <Rn>, #<imm8>
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auto result = ir.SubWithCarry(ir.GetRegister(n), ir.Imm32(imm32), ir.Imm1(1));
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ir.SetNFlag(ir.MostSignificantBit(result.result));
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ir.SetZFlag(ir.IsZero(result.result));
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ir.SetCFlag(result.carry);
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ir.SetVFlag(result.overflow);
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return true;
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}
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bool thumb1_AND_reg(Reg m, Reg d_n) {
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const Reg d = d_n, n = d_n;
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