thumb32: Implement QASX/UQASX
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4 changed files with 53 additions and 2 deletions
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@ -242,7 +242,7 @@ std::optional<std::reference_wrapper<const Thumb32Matcher<V>>> DecodeThumb32(u32
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INST(&V::thumb32_SADD8, "SADD8", "111110101000nnnn1111dddd0000mmmm"),
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INST(&V::thumb32_SSUB8, "SSUB8", "111110101100nnnn1111dddd0000mmmm"),
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INST(&V::thumb32_QADD16, "QADD16", "111110101001nnnn1111dddd0001mmmm"),
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//INST(&V::thumb32_QASX, "QASX", "111110101010----1111----0001----"),
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INST(&V::thumb32_QASX, "QASX", "111110101010nnnn1111dddd0001mmmm"),
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//INST(&V::thumb32_QSAX, "QSAX", "111110101110----1111----0001----"),
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//INST(&V::thumb32_QSUB16, "QSUB16", "111110101101----1111----0001----"),
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//INST(&V::thumb32_QADD8, "QADD8", "111110101000----1111----0001----"),
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@ -262,7 +262,7 @@ std::optional<std::reference_wrapper<const Thumb32Matcher<V>>> DecodeThumb32(u32
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INST(&V::thumb32_UADD8, "UADD8", "111110101000nnnn1111dddd0100mmmm"),
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INST(&V::thumb32_USUB8, "USUB8", "111110101100nnnn1111dddd0100mmmm"),
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INST(&V::thumb32_UQADD16, "UQADD16", "111110101001nnnn1111dddd0101mmmm"),
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//INST(&V::thumb32_UQASX, "UQASX", "111110101010----1111----0101----"),
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INST(&V::thumb32_UQASX, "UQASX", "111110101010nnnn1111dddd0101mmmm"),
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//INST(&V::thumb32_UQSAX, "UQSAX", "111110101110----1111----0101----"),
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//INST(&V::thumb32_UQSUB16, "UQSUB16", "111110101101----1111----0101----"),
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//INST(&V::thumb32_UQADD8, "UQADD8", "111110101000----1111----0101----"),
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@ -6,6 +6,13 @@
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#include "frontend/A32/translate/impl/translate_thumb.h"
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namespace Dynarmic::A32 {
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static IR::U32 Pack2x16To1x32(A32::IREmitter& ir, IR::U32 lo, IR::U32 hi) {
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return ir.Or(ir.And(lo, ir.Imm32(0xFFFF)), ir.LogicalShiftLeft(hi, ir.Imm8(16), ir.Imm1(0)).result);
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}
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static IR::U16 MostSignificantHalf(A32::IREmitter& ir, IR::U32 value) {
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return ir.LeastSignificantHalf(ir.LogicalShiftRight(value, ir.Imm8(16), ir.Imm1(0)).result);
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}
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bool ThumbTranslatorVisitor::thumb32_SADD8(Reg n, Reg d, Reg m) {
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC) {
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@ -188,6 +195,25 @@ bool ThumbTranslatorVisitor::thumb32_QADD16(Reg n, Reg d, Reg m) {
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_QASX(Reg n, Reg d, Reg m) {
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC) {
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return UnpredictableInstruction();
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}
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const auto Rn = ir.GetRegister(n);
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const auto Rm = ir.GetRegister(m);
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const auto Rn_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(Rn));
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const auto Rn_hi = ir.SignExtendHalfToWord(MostSignificantHalf(ir, Rn));
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const auto Rm_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(Rm));
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const auto Rm_hi = ir.SignExtendHalfToWord(MostSignificantHalf(ir, Rm));
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const auto diff = ir.SignedSaturation(ir.Sub(Rn_lo, Rm_hi), 16).result;
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const auto sum = ir.SignedSaturation(ir.Add(Rn_hi, Rm_lo), 16).result;
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const auto result = Pack2x16To1x32(ir, diff, sum);
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ir.SetRegister(d, result);
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_UQADD16(Reg n, Reg d, Reg m) {
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC) {
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return UnpredictableInstruction();
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@ -201,4 +227,23 @@ bool ThumbTranslatorVisitor::thumb32_UQADD16(Reg n, Reg d, Reg m) {
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_UQASX(Reg n, Reg d, Reg m) {
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC) {
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return UnpredictableInstruction();
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}
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const auto Rn = ir.GetRegister(n);
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const auto Rm = ir.GetRegister(m);
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const auto Rn_lo = ir.ZeroExtendHalfToWord(ir.LeastSignificantHalf(Rn));
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const auto Rn_hi = ir.ZeroExtendHalfToWord(MostSignificantHalf(ir, Rn));
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const auto Rm_lo = ir.ZeroExtendHalfToWord(ir.LeastSignificantHalf(Rm));
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const auto Rm_hi = ir.ZeroExtendHalfToWord(MostSignificantHalf(ir, Rm));
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const auto diff = ir.UnsignedSaturation(ir.Sub(Rn_lo, Rm_hi), 16).result;
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const auto sum = ir.UnsignedSaturation(ir.Add(Rn_hi, Rm_lo), 16).result;
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const auto result = Pack2x16To1x32(ir, diff, sum);
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ir.SetRegister(d, result);
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return true;
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}
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} // namespace Dynarmic::A32
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@ -143,7 +143,9 @@ struct ThumbTranslatorVisitor final {
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bool thumb32_USUB16(Reg n, Reg d, Reg m);
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bool thumb32_QADD16(Reg n, Reg d, Reg m);
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bool thumb32_QASX(Reg n, Reg d, Reg m);
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bool thumb32_UQADD16(Reg n, Reg d, Reg m);
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bool thumb32_UQASX(Reg n, Reg d, Reg m);
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};
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} // namespace Dynarmic::A32
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@ -380,6 +380,8 @@ TEST_CASE("Fuzz Thumb32 instructions set", "[JitX64][Thumb][Thumb32]") {
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three_reg_not_r15),
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ThumbInstGen("111110101001nnnn1111dddd0001mmmm", // QADD16
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three_reg_not_r15),
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ThumbInstGen("111110101010nnnn1111dddd0001mmmm", // QASX
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three_reg_not_r15),
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ThumbInstGen("111110101000nnnn1111dddd1001mmmm", // QDADD
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three_reg_not_r15),
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ThumbInstGen("111110101000nnnn1111dddd1011mmmm", // QDSUB
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@ -436,6 +438,8 @@ TEST_CASE("Fuzz Thumb32 instructions set", "[JitX64][Thumb][Thumb32]") {
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three_reg_not_r15),
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ThumbInstGen("111110101001nnnn1111dddd0101mmmm", // UQADD16
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three_reg_not_r15),
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ThumbInstGen("111110101010nnnn1111dddd0101mmmm", // UQASX
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three_reg_not_r15),
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ThumbInstGen("111110101110nnnn1111dddd0100mmmm", // USAX
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three_reg_not_r15),
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ThumbInstGen("111110101100nnnn1111dddd0100mmmm", // USUB8
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