A64: Fix bugs and address review comments
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3aeb7ca50c
commit
ae880d8391
2 changed files with 34 additions and 32 deletions
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@ -219,9 +219,9 @@ INST(LDTRB, "LDTRB", "00111
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INST(LDTRSB, "LDTRSB", "00111000oo0iiiiiiiii10nnnnnttttt")
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INST(STTRH, "STTRH", "01111000000iiiiiiiii10nnnnnttttt")
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INST(LDTRH, "LDTRH", "01111000010iiiiiiiii10nnnnnttttt")
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INST(LDTRSH, "LDTRSH", "011110001-0iiiiiiiii10nnnnnttttt")
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INST(STTR, "STTR", "1z111000000iiiiiiiii10nnnnnttttt")
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INST(LDTR, "LDTR", "1z111000010iiiiiiiii10nnnnnttttt")
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INST(LDTRSH, "LDTRSH", "01111000oo0iiiiiiiii10nnnnnttttt")
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INST(STTR, "STTR", "zz111000000iiiiiiiii10nnnnnttttt")
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INST(LDTR, "LDTR", "zz111000010iiiiiiiii10nnnnnttttt")
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INST(LDTRSW, "LDTRSW", "10111000100iiiiiiiii10nnnnnttttt")
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// Loads and stores - Atomic memory options
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@ -9,9 +9,9 @@
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namespace Dynarmic {
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namespace A64 {
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static bool store_register(TranslatorVisitor& tv, IREmitter& ir, const size_t datasize, Imm<9> imm9,
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Reg Rn, Reg Rt) {
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const u64 offset = imm9.ZeroExtend<u64>();
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static bool StoreRegister(TranslatorVisitor& tv, IREmitter& ir, const size_t datasize,
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const Imm<9> imm9, const Reg Rn, const Reg Rt) {
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const u64 offset = imm9.SignExtend<u64>();
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AccType acctype = AccType::UNPRIV;
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IR::U64 address;
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@ -27,9 +27,9 @@ static bool store_register(TranslatorVisitor& tv, IREmitter& ir, const size_t da
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return true;
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}
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static bool load_register(TranslatorVisitor& tv, IREmitter& ir, const size_t datasize, Imm<9> imm9,
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Reg Rn, Reg Rt) {
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const u64 offset = imm9.ZeroExtend<u64>();
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static bool LoadRegister(TranslatorVisitor& tv, IREmitter& ir, const size_t datasize,
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const Imm<9> imm9, const Reg Rn, const Reg Rt) {
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const u64 offset = imm9.SignExtend<u64>();
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AccType acctype = AccType::UNPRIV;
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IR::U64 address;
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@ -41,27 +41,29 @@ static bool load_register(TranslatorVisitor& tv, IREmitter& ir, const size_t dat
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}
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address = ir.Add(address, ir.Imm64(offset));
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IR::UAny data = tv.Mem(address, datasize / 8, acctype);
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tv.X(datasize, Rt, tv.ZeroExtend(data, 32));
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// max is used to zeroextend < 32 to 32, and > 32 to 64
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const size_t extended_size = std::max<size_t>(32, datasize);
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tv.X(extended_size, Rt, tv.ZeroExtend(data, extended_size));
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return true;
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}
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static bool load_register_signed(TranslatorVisitor& tv, IREmitter& ir, const size_t datasize,
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Imm<2> opc, Imm<9> imm9, Reg Rn, Reg Rt) {
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const u64 offset = imm9.ZeroExtend<u64>();
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static bool LoadRegisterSigned(TranslatorVisitor& tv, IREmitter& ir, const size_t datasize,
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const Imm<2> opc, const Imm<9> imm9, const Reg Rn, const Reg Rt) {
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const u64 offset = imm9.SignExtend<u64>();
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AccType acctype = AccType::UNPRIV;
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MemOp memop;
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bool signed_;
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bool is_signed;
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size_t regsize;
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if (opc.Bit<1>() == 0) {
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// store or zero-extending load
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memop = opc.Bit<0>() ? MemOp::LOAD : MemOp::STORE;
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regsize = 32;
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signed_ = false;
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is_signed = false;
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} else {
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// sign-extending load
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memop = MemOp::LOAD;
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regsize = opc.Bit<0>() ? 32 : 64;
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signed_ = true;
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is_signed = true;
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}
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IR::U64 address;
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@ -78,11 +80,11 @@ static bool load_register_signed(TranslatorVisitor& tv, IREmitter& ir, const siz
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tv.Mem(address, datasize / 8, acctype, tv.X(datasize, Rt));
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break;
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case MemOp::LOAD: {
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IR::U8 data = tv.Mem(address, datasize / 8, acctype);
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if (signed_) {
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tv.X(datasize, Rt, tv.SignExtend(data, regsize));
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IR::UAny data = tv.Mem(address, datasize / 8, acctype);
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if (is_signed) {
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tv.X(regsize, Rt, tv.SignExtend(data, regsize));
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} else {
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tv.X(datasize, Rt, tv.ZeroExtend(data, regsize));
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tv.X(regsize, Rt, tv.ZeroExtend(data, regsize));
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}
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break;
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}
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@ -94,39 +96,39 @@ static bool load_register_signed(TranslatorVisitor& tv, IREmitter& ir, const siz
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}
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bool TranslatorVisitor::STTRB(Imm<9> imm9, Reg Rn, Reg Rt) {
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return store_register(*this, ir, 8, imm9, Rn, Rt);
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return StoreRegister(*this, ir, 8, imm9, Rn, Rt);
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}
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bool TranslatorVisitor::STTRH(Imm<9> imm9, Reg Rn, Reg Rt) {
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return store_register(*this, ir, 16, imm9, Rn, Rt);
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return StoreRegister(*this, ir, 16, imm9, Rn, Rt);
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}
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bool TranslatorVisitor::STTR(Imm<2> size, Imm<9> imm9, Reg Rn, Reg Rt) {
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const size_t scale = size.ZeroExtend<size_t>();
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const size_t datasize = 8 << scale;
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return store_register(*this, ir, datasize, imm9, Rn, Rt);
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return StoreRegister(*this, ir, datasize, imm9, Rn, Rt);
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}
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bool TranslatorVisitor::LDTRB(Imm<9> imm9, Reg Rn, Reg Rt) {
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return load_register(*this, ir, 8, imm9, Rn, Rt);
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return LoadRegister(*this, ir, 8, imm9, Rn, Rt);
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}
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bool TranslatorVisitor::LDTRH(Imm<9> imm9, Reg Rn, Reg Rt) {
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return load_register(*this, ir, 16, imm9, Rn, Rt);
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return LoadRegister(*this, ir, 16, imm9, Rn, Rt);
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}
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bool TranslatorVisitor::LDTR(Imm<2> size, Imm<9> imm9, Reg Rn, Reg Rt) {
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const size_t scale = size.ZeroExtend<size_t>();
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const size_t datasize = 8 << scale;
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return load_register(*this, ir, datasize, imm9, Rn, Rt);
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return LoadRegister(*this, ir, datasize, imm9, Rn, Rt);
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}
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bool TranslatorVisitor::LDTRSB(Imm<2> opc, Imm<9> imm9, Reg Rn, Reg Rt) {
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return load_register_signed(*this, ir, 8, opc, imm9, Rn, Rt);
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return LoadRegisterSigned(*this, ir, 8, opc, imm9, Rn, Rt);
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}
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bool TranslatorVisitor::LDTRSH(Imm<2> opc, Imm<9> imm9, Reg Rn, Reg Rt) {
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return load_register_signed(*this, ir, 16, opc, imm9, Rn, Rt);
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return LoadRegisterSigned(*this, ir, 16, opc, imm9, Rn, Rt);
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}
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bool TranslatorVisitor::LDTRSW(Imm<9> imm9, Reg Rn, Reg Rt) {
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@ -136,14 +138,14 @@ bool TranslatorVisitor::LDTRSW(Imm<9> imm9, Reg Rn, Reg Rt) {
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if (Rn == Reg::SP) {
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// TODO: Check Stack Alignment
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address = SP(32);
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address = SP(64);
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} else {
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address = X(32, Rn);
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address = X(64, Rn);
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}
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address = ir.Add(address, ir.Imm64(offset));
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IR::UAny data = Mem(address, 4, acctype);
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X(32, Rt, SignExtend(data, 64));
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X(64, Rt, SignExtend(data, 64));
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return true;
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}
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} // namespace A64
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} // namespace Dynarmic
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} // namespace Dynarmic
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