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translate_arm/vfp2: Implement VLDM (A1, A2)

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This commit is contained in:
MerryMage 2016-08-23 14:27:49 +01:00
parent d5805cc6eb
commit af9a68f0d1
4 changed files with 83 additions and 2 deletions
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4
src/frontend/decoder/vfp2.h
View file

@ -102,8 +102,8 @@ boost::optional<const VFP2Matcher<V>&> DecodeVFP2(u32 instruction) {
INST(&V::vfp2_VPOP, "VPOP", "cccc11001D111101dddd101zvvvvvvvv"), INST(&V::vfp2_VPOP, "VPOP", "cccc11001D111101dddd101zvvvvvvvv"),
INST(&V::vfp2_VLDR, "VLDR", "cccc1101UD01nnnndddd101zvvvvvvvv"), INST(&V::vfp2_VLDR, "VLDR", "cccc1101UD01nnnndddd101zvvvvvvvv"),
INST(&V::vfp2_VSTR, "VSTR", "cccc1101UD00nnnndddd101zvvvvvvvv"), INST(&V::vfp2_VSTR, "VSTR", "cccc1101UD00nnnndddd101zvvvvvvvv"),
// VLDM INST(&V::vfp2_VLDM_a1, "VLDM (A1)", "cccc110puDw1nnnndddd1011vvvvvvvv"),
// VLDMDB INST(&V::vfp2_VLDM_a2, "VLDM (A2)", "cccc110puDw1nnnndddd1010vvvvvvvv"),
#undef INST #undef INST

13
src/frontend/disassembler/disassembler_arm.cpp
View file

@ -889,6 +889,19 @@ public:
return Common::StringFromFormat("vstr%s %s, [%s, #%c%u]", CondToString(cond), FPRegStr(sz, Vd, D).c_str(), RegToString(n), U ? '+' : '-', imm32); return Common::StringFromFormat("vstr%s %s, [%s, #%c%u]", CondToString(cond), FPRegStr(sz, Vd, D).c_str(), RegToString(n), U ? '+' : '-', imm32);
} }
std::string vfp2_VLDM_a1(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm8 imm8) {
const char* mode = "<invalid mode>";
if (!p && u) mode = "ia";
if (p && !u) mode = "db";
return Common::StringFromFormat("vldm%s%s.f64 %s%s, %s(+%u)", mode, CondToString(cond), RegToString(n), w ? "!" : "", FPRegStr(true, Vd, D).c_str(), imm8);
}
std::string vfp2_VLDM_a2(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm8 imm8) {
const char* mode = "<invalid mode>";
if (!p && u) mode = "ia";
if (p && !u) mode = "db";
return Common::StringFromFormat("vldm%s%s.f32 %s%s, %s(+%u)", mode, CondToString(cond), RegToString(n), w ? "!" : "", FPRegStr(false, Vd, D).c_str(), imm8);
}
}; };

2
src/frontend/translate/translate_arm/translate_arm.h
View file

@ -363,6 +363,8 @@ struct ArmTranslatorVisitor final {
bool vfp2_VSTR(Cond cond, bool U, bool D, Reg n, size_t Vd, bool sz, Imm8 imm8); bool vfp2_VSTR(Cond cond, bool U, bool D, Reg n, size_t Vd, bool sz, Imm8 imm8);
bool vfp2_VPOP(Cond cond, bool D, size_t Vd, bool sz, Imm8 imm8); bool vfp2_VPOP(Cond cond, bool D, size_t Vd, bool sz, Imm8 imm8);
bool vfp2_VPUSH(Cond cond, bool D, size_t Vd, bool sz, Imm8 imm8); bool vfp2_VPUSH(Cond cond, bool D, size_t Vd, bool sz, Imm8 imm8);
bool vfp2_VLDM_a1(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm8 imm8);
bool vfp2_VLDM_a2(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm8 imm8);
}; };
} // namespace Arm } // namespace Arm

66
src/frontend/translate/translate_arm/vfp2.cpp
View file

@ -467,5 +467,71 @@ bool ArmTranslatorVisitor::vfp2_VSTR(Cond cond, bool U, bool D, Reg n, size_t Vd
return true; return true;
} }
bool ArmTranslatorVisitor::vfp2_VLDM_a1(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm8 imm8) {
if (!p && !u && !w)
ASSERT_MSG(false, "Decode error");
if (p && !w)
ASSERT_MSG(false, "Decode error");
if (p == u && w)
return arm_UDF();
if (n == Reg::PC && w)
return UnpredictableInstruction();
ExtReg d = ToExtReg(true, Vd, D);
u32 imm32 = imm8 << 2;
size_t regs = imm8;
if (regs == 0 || regs > 16 || Arm::RegNumber(d)+regs > 32)
return UnpredictableInstruction();
// VLDM<mode>.F64 <Rn>{!}, <list of double registers>
if (ConditionPassed(cond)) {
auto address = u ? ir.GetRegister(n) : ir.Sub(ir.GetRegister(n), ir.Imm32(imm32));
if (w)
ir.SetRegister(n, u ? ir.Add(address, ir.Imm32(imm32)) : address);
for (size_t i = 0; i < regs; i++) {
auto word1 = ir.ReadMemory32(address);
address = ir.Add(address, ir.Imm32(4));
auto word2 = ir.ReadMemory32(address);
address = ir.Add(address, ir.Imm32(4));
if (ir.current_location.EFlag()) std::swap(word1, word2);
ir.SetExtendedRegister(d + i, ir.TransferToFP64(ir.Pack2x32To1x64(word1, word2)));
}
}
return true;
}
bool ArmTranslatorVisitor::vfp2_VLDM_a2(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm8 imm8) {
if (!p && !u && !w)
ASSERT_MSG(false, "Decode error");
if (p && !w)
ASSERT_MSG(false, "Decode error");
if (p == u && w)
return arm_UDF();
if (n == Reg::PC && w)
return UnpredictableInstruction();
ExtReg d = ToExtReg(false, Vd, D);
u32 imm32 = imm8 << 2;
size_t regs = imm8;
if (regs == 0 || Arm::RegNumber(d)+regs > 32)
return UnpredictableInstruction();
// VLDM<mode>.F32 <Rn>{!}, <list of single registers>
if (ConditionPassed(cond)) {
auto address = u ? ir.GetRegister(n) : ir.Sub(ir.GetRegister(n), ir.Imm32(imm32));
if (w)
ir.SetRegister(n, u ? ir.Add(address, ir.Imm32(imm32)) : address);
for (size_t i = 0; i < regs; i++) {
auto word = ir.ReadMemory32(address);
address = ir.Add(address, ir.Imm32(4));
ir.SetExtendedRegister(d + i, ir.TransferToFP32(word));
}
}
return true;
}
} // namespace Arm } // namespace Arm
} // namespace Dynarmic } // namespace Dynarmic