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thumb32: Implement SHSUB16/UHSUB16

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This commit is contained in:
Lioncash 2021-02-01 17:21:24 -05:00
parent 51b7c32d02
commit afad76078d
4 changed files with 34 additions and 2 deletions
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4
src/frontend/A32/decoder/thumb32.h
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@ -250,7 +250,7 @@ std::optional<std::reference_wrapper<const Thumb32Matcher<V>>> DecodeThumb32(u32
INST(&V::thumb32_SHADD16, "SHADD16", "111110101001nnnn1111dddd0010mmmm"),
INST(&V::thumb32_SHASX, "SHASX", "111110101010nnnn1111dddd0010mmmm"),
INST(&V::thumb32_SHSAX, "SHSAX", "111110101110nnnn1111dddd0010mmmm"),
//INST(&V::thumb32_SHSUB16, "SHSUB16", "111110101101----1111----0010----"),
INST(&V::thumb32_SHSUB16, "SHSUB16", "111110101101nnnn1111dddd0010mmmm"),
//INST(&V::thumb32_SHADD8, "SHADD8", "111110101000----1111----0010----"),
//INST(&V::thumb32_SHSUB8, "SHSUB8", "111110101100----1111----0010----"),
@ -270,7 +270,7 @@ std::optional<std::reference_wrapper<const Thumb32Matcher<V>>> DecodeThumb32(u32
INST(&V::thumb32_UHADD16, "UHADD16", "111110101001nnnn1111dddd0110mmmm"),
INST(&V::thumb32_UHASX, "UHASX", "111110101010nnnn1111dddd0110mmmm"),
INST(&V::thumb32_UHSAX, "UHSAX", "111110101110nnnn1111dddd0110mmmm"),
//INST(&V::thumb32_UHSUB16, "UHSUB16", "111110101101----1111----0110----"),
INST(&V::thumb32_UHSUB16, "UHSUB16", "111110101101nnnn1111dddd0110mmmm"),
//INST(&V::thumb32_UHADD8, "UHADD8", "111110101000----1111----0110----"),
//INST(&V::thumb32_UHSUB8, "UHSUB8", "111110101100----1111----0110----"),

26
src/frontend/A32/translate/impl/thumb32_parallel.cpp
View file

@ -401,6 +401,19 @@ bool ThumbTranslatorVisitor::thumb32_SHSAX(Reg n, Reg d, Reg m) {
return true;
}
bool ThumbTranslatorVisitor::thumb32_SHSUB16(Reg n, Reg d, Reg m) {
if (d == Reg::PC || n == Reg::PC || m == Reg::PC) {
return UnpredictableInstruction();
}
const auto reg_m = ir.GetRegister(m);
const auto reg_n = ir.GetRegister(n);
const auto result = ir.PackedHalvingSubS16(reg_n, reg_m);
ir.SetRegister(d, result);
return true;
}
bool ThumbTranslatorVisitor::thumb32_UHADD16(Reg n, Reg d, Reg m) {
if (d == Reg::PC || n == Reg::PC || m == Reg::PC) {
return UnpredictableInstruction();
@ -440,4 +453,17 @@ bool ThumbTranslatorVisitor::thumb32_UHSAX(Reg n, Reg d, Reg m) {
return true;
}
bool ThumbTranslatorVisitor::thumb32_UHSUB16(Reg n, Reg d, Reg m) {
if (d == Reg::PC || n == Reg::PC || m == Reg::PC) {
return UnpredictableInstruction();
}
const auto reg_m = ir.GetRegister(m);
const auto reg_n = ir.GetRegister(n);
const auto result = ir.PackedHalvingSubU16(reg_n, reg_m);
ir.SetRegister(d, result);
return true;
}
} // namespace Dynarmic::A32

2
src/frontend/A32/translate/impl/translate_thumb.h
View file

@ -158,9 +158,11 @@ struct ThumbTranslatorVisitor final {
bool thumb32_SHADD16(Reg n, Reg d, Reg m);
bool thumb32_SHASX(Reg n, Reg d, Reg m);
bool thumb32_SHSAX(Reg n, Reg d, Reg m);
bool thumb32_SHSUB16(Reg n, Reg d, Reg m);
bool thumb32_UHADD16(Reg n, Reg d, Reg m);
bool thumb32_UHASX(Reg n, Reg d, Reg m);
bool thumb32_UHSAX(Reg n, Reg d, Reg m);
bool thumb32_UHSUB16(Reg n, Reg d, Reg m);
};
} // namespace Dynarmic::A32

4
tests/A32/fuzz_thumb.cpp
View file

@ -438,6 +438,8 @@ TEST_CASE("Fuzz Thumb32 instructions set", "[JitX64][Thumb][Thumb32]") {
three_reg_not_r15),
ThumbInstGen("111110101110nnnn1111dddd0010mmmm", // SHSAX
three_reg_not_r15),
ThumbInstGen("111110101101nnnn1111dddd0010mmmm", // SHSUB16
three_reg_not_r15),
ThumbInstGen("111110101110nnnn1111dddd0000mmmm", // SSAX
three_reg_not_r15),
ThumbInstGen("111110101100nnnn1111dddd0000mmmm", // SSUB8
@ -456,6 +458,8 @@ TEST_CASE("Fuzz Thumb32 instructions set", "[JitX64][Thumb][Thumb32]") {
three_reg_not_r15),
ThumbInstGen("111110101110nnnn1111dddd0110mmmm", // UHSAX
three_reg_not_r15),
ThumbInstGen("111110101101nnnn1111dddd0110mmmm", // UHSUB16
three_reg_not_r15),
ThumbInstGen("111110101000nnnn1111dddd0101mmmm", // UQADD8
three_reg_not_r15),
ThumbInstGen("111110101001nnnn1111dddd0101mmmm", // UQADD16