A64: Implement STLRB, STLRH, STLR, LDARB, LDARH, LDAR
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MerryMage
parent
5a65313236
commit
b02b861242
4 changed files with 91 additions and 58 deletions
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@ -82,6 +82,7 @@ add_library(dynarmic
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frontend/A64/translate/impl/floating_point_data_processing_two_register.cpp
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frontend/A64/translate/impl/impl.cpp
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frontend/A64/translate/impl/impl.h
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frontend/A64/translate/impl/load_store_exclusive.cpp
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frontend/A64/translate/impl/load_store_load_literal.cpp
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frontend/A64/translate/impl/load_store_multiple_structures.cpp
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frontend/A64/translate/impl/load_store_register_immediate.cpp
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@ -124,38 +124,22 @@ INST(LDx_mult_2, "LDx (multiple structures)", "0Q001
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//INST(LD4R_2, "LD4R", "0Q001101111mmmmm1110zznnnnnttttt")
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// Loads and stores - Load/Store Exclusive
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//INST(STXRB, "STXRB", "00001000000sssss011111nnnnnttttt")
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//INST(STLXRB, "STLXRB", "00001000000sssss111111nnnnnttttt")
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//INST(CASP, "CASP, CASPA, CASPAL, CASPL", "0z0010000L1sssssp11111nnnnnttttt")
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//INST(LDXRB, "LDXRB", "0000100001011111011111nnnnnttttt")
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//INST(LDAXRB, "LDAXRB", "0000100001011111111111nnnnnttttt")
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//INST(STLLRB, "STLLRB", "0000100010011111011111nnnnnttttt")
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//INST(STLRB, "STLRB", "0000100010011111111111nnnnnttttt")
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//INST(CASB, "CASB, CASAB, CASALB, CASLB", "000010001L1sssssp11111nnnnnttttt")
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//INST(LDLARB, "LDLARB", "0000100011011111011111nnnnnttttt")
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//INST(LDARB, "LDARB", "0000100011011111111111nnnnnttttt")
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//INST(STXRH, "STXRH", "01001000000sssss011111nnnnnttttt")
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//INST(STLXRH, "STLXRH", "01001000000sssss111111nnnnnttttt")
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//INST(LDXRH, "LDXRH", "0100100001011111011111nnnnnttttt")
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//INST(LDAXRH, "LDAXRH", "0100100001011111111111nnnnnttttt")
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//INST(STLLRH, "STLLRH", "0100100010011111011111nnnnnttttt")
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//INST(STLRH, "STLRH", "0100100010011111111111nnnnnttttt")
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//INST(CASH, "CASH, CASAH, CASALH, CASLH", "010010001L1sssssp11111nnnnnttttt")
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//INST(LDLARH, "LDLARH", "0100100011011111011111nnnnnttttt")
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//INST(LDARH, "LDARH", "0100100011011111111111nnnnnttttt")
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//INST(STXR, "STXR", "1-001000000sssss011111nnnnnttttt")
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//INST(STLXR, "STLXR", "1-001000000sssss111111nnnnnttttt")
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//INST(STXR, "STXRB, STXRH, STXR", "zz001000000sssss011111nnnnnttttt")
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//INST(STLXR, "STLXRB, STLXRH, STLXR", "zz001000000sssss111111nnnnnttttt")
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//INST(STXP, "STXP", "1z001000001sssss0uuuuunnnnnttttt")
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//INST(STLXP, "STLXP", "1z001000001sssss1uuuuunnnnnttttt")
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//INST(LDXR, "LDXR", "1-00100001011111011111nnnnnttttt")
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//INST(LDAXR, "LDAXR", "1-00100001011111111111nnnnnttttt")
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//INST(LDXR, "LDXRB, LDXRH, LDXR", "zz00100001011111011111nnnnnttttt")
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//INST(LDAXRB, "LDAXRB", "zz00100001011111111111nnnnnttttt")
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//INST(LDXP, "LDXP", "1z001000011111110uuuuunnnnnttttt")
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//INST(LDAXP, "LDAXP", "1z001000011111111uuuuunnnnnttttt")
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//INST(STLLR, "STLLR", "1-00100010011111011111nnnnnttttt")
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//INST(STLR, "STLR", "1-00100010011111111111nnnnnttttt")
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//INST(CAS, "CAS, CASA, CASAL, CASL", "1-0010001L1sssssp11111nnnnnttttt")
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//INST(LDLAR, "LDLAR", "1-00100011011111011111nnnnnttttt")
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//INST(LDAR, "LDAR", "1-00100011011111111111nnnnnttttt")
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//INST(STLLR, "STLLRB, STLLRH, STLLR", "zz00100010011111011111nnnnnttttt")
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INST(STLR, "STLRB, STLRH, STLR", "zz00100010011111111111nnnnnttttt")
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//INST(LDLAR, "LDLARB, LDLARH, LDLAR", "zz00100011011111011111nnnnnttttt")
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INST(LDAR, "LDARB, LDARH, LDAR", "zz00100011011111111111nnnnnttttt")
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//INST(CASP, "CASP, CASPA, CASPAL, CASPL", "0z0010000L1sssssp11111nnnnnttttt") // ARMv8.1
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//INST(CASB, "CASB, CASAB, CASALB, CASLB", "000010001L1sssssp11111nnnnnttttt") // ARMv8.1
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//INST(CASH, "CASH, CASAH, CASALH, CASLH", "010010001L1sssssp11111nnnnnttttt") // ARMv8.1
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//INST(CAS, "CAS, CASA, CASAL, CASL", "1z0010001L1sssssp11111nnnnnttttt") // ARMv8.1
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// Loads and stores - Load register (literal)
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INST(LDR_lit_gen, "LDR (literal)", "0z011000iiiiiiiiiiiiiiiiiiittttt")
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@ -16,7 +16,7 @@
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namespace Dynarmic::A64 {
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enum class AccType {
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NORMAL, VEC, STREAM, VECSTREAM, ATOMIC, ORDERED, UNPRIV, IFETCH, PTW, DC, IC, AT,
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NORMAL, VEC, STREAM, VECSTREAM, ATOMIC, ORDERED, ORDEREDRW, LIMITEDORDERED, UNPRIV, IFETCH, PTW, DC, IC, DCZVA, AT,
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};
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enum class MemOp {
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@ -187,38 +187,22 @@ struct TranslatorVisitor final {
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bool LD4R_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Vec Vt);
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// Loads and stores - Load/Store Exclusive
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bool STXRB(Reg Rs, Reg Rn, Reg Rt);
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bool STLXRB(Reg Rs, Reg Rn, Reg Rt);
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bool STXR(Imm<2> size, Reg Rs, Reg Rn, Reg Rt);
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bool STLXR(Imm<2> size, Reg Rs, Reg Rn, Reg Rt);
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bool STXP(Imm<1> size, Reg Rs, Reg Rt2, Reg Rn, Reg Rt);
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bool STLXP(Imm<1> size, Reg Rs, Reg Rt2, Reg Rn, Reg Rt);
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bool LDXR(Imm<2> size, Reg Rn, Reg Rt);
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bool LDAXRB(Imm<2> size, Reg Rn, Reg Rt);
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bool LDXP(Imm<1> size, Reg Rt2, Reg Rn, Reg Rt);
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bool LDAXP(Imm<1> size, Reg Rt2, Reg Rn, Reg Rt);
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bool STLLR(Imm<2> size, Reg Rn, Reg Rt);
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bool STLR(Imm<2> size, Reg Rn, Reg Rt);
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bool LDLAR(Imm<2> size, Reg Rn, Reg Rt);
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bool LDAR(Imm<2> size, Reg Rn, Reg Rt);
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bool CASP(bool sz, bool L, Reg Rs, bool o0, Reg Rn, Reg Rt);
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bool LDXRB(Reg Rn, Reg Rt);
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bool LDAXRB(Reg Rn, Reg Rt);
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bool STLLRB(Reg Rn, Reg Rt);
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bool STLRB(Reg Rn, Reg Rt);
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bool CASB(bool L, Reg Rs, bool o0, Reg Rn, Reg Rt);
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bool LDLARB(Reg Rn, Reg Rt);
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bool LDARB(Reg Rn, Reg Rt);
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bool STXRH(Reg Rs, Reg Rn, Reg Rt);
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bool STLXRH(Reg Rs, Reg Rn, Reg Rt);
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bool LDXRH(Reg Rn, Reg Rt);
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bool LDAXRH(Reg Rn, Reg Rt);
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bool STLLRH(Reg Rn, Reg Rt);
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bool STLRH(Reg Rn, Reg Rt);
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bool CASH(bool L, Reg Rs, bool o0, Reg Rn, Reg Rt);
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bool LDLARH(Reg Rn, Reg Rt);
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bool LDARH(Reg Rn, Reg Rt);
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bool STXR(Reg Rs, Reg Rn, Reg Rt);
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bool STLXR(Reg Rs, Reg Rn, Reg Rt);
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bool STXP(bool sz, Reg Rs, Reg Rt2, Reg Rn, Reg Rt);
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bool STLXP(bool sz, Reg Rs, Reg Rt2, Reg Rn, Reg Rt);
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bool LDXR(Reg Rn, Reg Rt);
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bool LDAXR(Reg Rn, Reg Rt);
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bool LDXP(bool sz, Reg Rt2, Reg Rn, Reg Rt);
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bool LDAXP(bool sz, Reg Rt2, Reg Rn, Reg Rt);
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bool STLLR(Reg Rn, Reg Rt);
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bool STLR(Reg Rn, Reg Rt);
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bool CAS(bool L, Reg Rs, bool o0, Reg Rn, Reg Rt);
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bool LDLAR(Reg Rn, Reg Rt);
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bool LDAR(Reg Rn, Reg Rt);
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bool CAS(bool sz, bool L, Reg Rs, bool o0, Reg Rn, Reg Rt);
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// Loads and stores - Load register (literal)
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bool LDR_lit_gen(bool opc_0, Imm<19> imm19, Reg Rt);
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64
src/frontend/A64/translate/impl/load_store_exclusive.cpp
Normal file
64
src/frontend/A64/translate/impl/load_store_exclusive.cpp
Normal file
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@ -0,0 +1,64 @@
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/* This file is part of the dynarmic project.
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* Copyright (c) 2018 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#include "frontend/A64/translate/impl/impl.h"
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namespace Dynarmic::A64 {
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static bool OrderedSharedDecodeAndOperation(TranslatorVisitor& tv, size_t size, bool L, bool o0, Reg Rn, Reg Rt) {
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// Shared Decode
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const AccType acctype = !o0 ? AccType::LIMITEDORDERED : AccType::ORDERED;
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const MemOp memop = L ? MemOp::LOAD : MemOp::STORE;
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const size_t elsize = 8 << size;
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const size_t regsize = elsize == 64 ? 64 : 32;
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const size_t datasize = elsize;
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// Operation
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const size_t dbytes = datasize / 8;
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IR::U64 address;
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if (Rn == Reg::SP) {
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// TODO: Check SP Alignment
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address = tv.SP(64);
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} else {
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address = tv.X(64, Rn);
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}
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switch (memop) {
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case MemOp::STORE: {
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IR::UAny data = tv.X(datasize, Rt);
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tv.Mem(address, dbytes, acctype, data);
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break;
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}
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case MemOp::LOAD: {
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IR::UAny data = tv.Mem(address, dbytes, acctype);
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tv.X(regsize, Rt, tv.ZeroExtend(data, regsize));
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break;
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}
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default:
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UNREACHABLE();
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}
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return true;
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}
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bool TranslatorVisitor::STLR(Imm<2> sz, Reg Rn, Reg Rt) {
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const size_t size = sz.ZeroExtend<size_t>();
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const bool L = 0;
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const bool o0 = 1;
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return OrderedSharedDecodeAndOperation(*this, size, L, o0, Rn, Rt);
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}
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bool TranslatorVisitor::LDAR(Imm<2> sz, Reg Rn, Reg Rt) {
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const size_t size = sz.ZeroExtend<size_t>();
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const bool L = 1;
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const bool o0 = 1;
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return OrderedSharedDecodeAndOperation(*this, size, L, o0, Rn, Rt);
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}
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} // namespace Dynarmic::A64
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