thumb32: Add coprocessor instructions
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MerryMage
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5ebe11c329
commit
b93ae62acf
5 changed files with 95 additions and 16 deletions
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@ -157,6 +157,7 @@ if ("A32" IN_LIST DYNARMIC_FRONTENDS)
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frontend/A32/translate/impl/thumb16.cpp
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frontend/A32/translate/impl/thumb32_branch.cpp
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frontend/A32/translate/impl/thumb32_control.cpp
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frontend/A32/translate/impl/thumb32_coprocessor.cpp
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frontend/A32/translate/impl/thumb32_data_processing_modified_immediate.cpp
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frontend/A32/translate/impl/thumb32_data_processing_plain_binary_immediate.cpp
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frontend/A32/translate/impl/thumb32_data_processing_register.cpp
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@ -281,19 +281,10 @@ INST(thumb32_UMLAL, "UMLAL", "111110111110nnnnllllhh
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INST(thumb32_UMAAL, "UMAAL", "111110111110nnnnllllhhhh0110mmmm")
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// Coprocessor
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//INST(thumb32_MCRR2, "MCRR2", "111111000100--------------------")
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//INST(thumb32_MCRR, "MCRR", "111011000100--------------------")
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//INST(thumb32_STC2, "STC2", "1111110----0--------------------")
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//INST(thumb32_STC, "STC", "1110110----0--------------------")
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//INST(thumb32_MRRC2, "MRRC2", "111111000101--------------------")
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//INST(thumb32_MRRC, "MRRC", "111011000101--------------------")
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//INST(thumb32_LDC2_lit, "LDC2 (lit)", "1111110----11111----------------")
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//INST(thumb32_LDC_lit, "LDC (lit)", "1110110----11111----------------")
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//INST(thumb32_LDC2_imm, "LDC2 (imm)", "1111110----1--------------------")
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//INST(thumb32_LDC_imm, "LDC (imm)", "1110110----1--------------------")
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//INST(thumb32_CDP2, "CDP2", "11111110-------------------0----")
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//INST(thumb32_CDP, "CDP", "11101110-------------------0----")
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//INST(thumb32_MCR2, "MCR2", "11111110---0---------------1----")
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//INST(thumb32_MCR, "MCR", "11101110---0---------------1----")
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//INST(thumb32_MRC2, "MRC2", "11111110---1---------------1----")
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//INST(thumb32_MRC, "MRC", "11101110---1---------------1----")
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INST(thumb32_MCRR, "MCRR", "111o11000100uuuuttttppppooooMMMM")
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INST(thumb32_MRRC, "MRRC", "111o11000101uuuuttttppppooooMMMM")
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INST(thumb32_STC, "STC", "111o110pudw0nnnnDDDDppppvvvvvvvv")
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INST(thumb32_LDC, "LDC", "111o110pudw1nnnnDDDDppppvvvvvvvv")
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INST(thumb32_CDP, "CDP", "111o1110ooooNNNNDDDDppppooo0MMMM")
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INST(thumb32_MCR, "MCR", "111o1110ooo0NNNNttttppppooo1MMMM")
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INST(thumb32_MRC, "MRC", "111o1110ooo1NNNNttttppppooo1MMMM")
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75
src/frontend/A32/translate/impl/thumb32_coprocessor.cpp
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75
src/frontend/A32/translate/impl/thumb32_coprocessor.cpp
Normal file
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@ -0,0 +1,75 @@
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/* This file is part of the dynarmic project.
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* Copyright (c) 2021 MerryMage
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* SPDX-License-Identifier: 0BSD
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*/
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#include "frontend/A32/translate/impl/translate.h"
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namespace Dynarmic::A32 {
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bool TranslatorVisitor::thumb32_MCRR(bool two, Reg t2, Reg t, size_t coproc_no, size_t opc, CoprocReg CRm) {
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ir.CoprocSendTwoWords(coproc_no, two, opc, CRm, ir.GetRegister(t), ir.GetRegister(t2));
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return true;
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}
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bool TranslatorVisitor::thumb32_MRRC(bool two, Reg t2, Reg t, size_t coproc_no, size_t opc, CoprocReg CRm) {
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const auto two_words = ir.CoprocGetTwoWords(coproc_no, two, opc, CRm);
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ir.SetRegister(t, ir.LeastSignificantWord(two_words));
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ir.SetRegister(t2, ir.MostSignificantWord(two_words).result);
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return true;
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}
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bool TranslatorVisitor::thumb32_STC(bool two, bool p, bool u, bool d, bool w, Reg n, CoprocReg CRd, size_t coproc_no, Imm<8> imm8) {
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const u32 imm32 = imm8.ZeroExtend() << 2;
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const bool index = p;
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const bool add = u;
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const bool wback = w;
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const bool has_option = !p && !w && u;
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const IR::U32 reg_n = ir.GetRegister(n);
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const IR::U32 offset_address = add ? ir.Add(reg_n, ir.Imm32(imm32)) : ir.Sub(reg_n, ir.Imm32(imm32));
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const IR::U32 address = index ? offset_address : reg_n;
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ir.CoprocStoreWords(coproc_no, two, d, CRd, address, has_option, imm8.ZeroExtend<u8>());
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if (wback) {
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ir.SetRegister(n, offset_address);
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}
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return true;
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}
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bool TranslatorVisitor::thumb32_LDC(bool two, bool p, bool u, bool d, bool w, Reg n, CoprocReg CRd, size_t coproc_no, Imm<8> imm8) {
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const u32 imm32 = imm8.ZeroExtend() << 2;
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const bool index = p;
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const bool add = u;
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const bool wback = w;
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const bool has_option = !p && !w && u;
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const IR::U32 reg_n = ir.GetRegister(n);
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const IR::U32 offset_address = add ? ir.Add(reg_n, ir.Imm32(imm32)) : ir.Sub(reg_n, ir.Imm32(imm32));
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const IR::U32 address = index ? offset_address : reg_n;
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ir.CoprocLoadWords(coproc_no, two, d, CRd, address, has_option, imm8.ZeroExtend<u8>());
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if (wback) {
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ir.SetRegister(n, offset_address);
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}
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return true;
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}
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bool TranslatorVisitor::thumb32_CDP(bool two, size_t opc1, CoprocReg CRn, CoprocReg CRd, size_t coproc_no, size_t opc2, CoprocReg CRm) {
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ir.CoprocInternalOperation(coproc_no, two, opc1, CRd, CRn, CRm, opc2);
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return true;
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}
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bool TranslatorVisitor::thumb32_MCR(bool two, size_t opc1, CoprocReg CRn, Reg t, size_t coproc_no, size_t opc2, CoprocReg CRm) {
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ir.CoprocSendOneWord(coproc_no, two, opc1, CRn, CRm, opc2, ir.GetRegister(t));
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return true;
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}
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bool TranslatorVisitor::thumb32_MRC(bool two, size_t opc1, CoprocReg CRn, Reg t, size_t coproc_no, size_t opc2, CoprocReg CRm) {
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const auto word = ir.CoprocGetOneWord(coproc_no, two, opc1, CRn, CRm, opc2);
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if (t != Reg::PC) {
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ir.SetRegister(t, word);
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} else {
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const auto new_cpsr_nzcv = ir.And(word, ir.Imm32(0xF0000000));
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ir.SetCpsrNZCV(new_cpsr_nzcv);
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}
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return true;
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}
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} // namespace Dynarmic::A32
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@ -740,6 +740,15 @@ struct TranslatorVisitor final {
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bool thumb32_UHSUB8(Reg n, Reg d, Reg m);
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bool thumb32_UHSUB16(Reg n, Reg d, Reg m);
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// thumb32 coprocessor insturctions
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bool thumb32_MCRR(bool two, Reg t2, Reg t, size_t coproc_no, size_t opc, CoprocReg CRm);
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bool thumb32_MRRC(bool two, Reg t2, Reg t, size_t coproc_no, size_t opc, CoprocReg CRm);
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bool thumb32_STC(bool two, bool p, bool u, bool d, bool w, Reg n, CoprocReg CRd, size_t coproc_no, Imm<8> imm8);
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bool thumb32_LDC(bool two, bool p, bool u, bool d, bool w, Reg n, CoprocReg CRd, size_t coproc_no, Imm<8> imm8);
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bool thumb32_CDP(bool two, size_t opc1, CoprocReg CRn, CoprocReg CRd, size_t coproc_no, size_t opc2, CoprocReg CRm);
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bool thumb32_MCR(bool two, size_t opc1, CoprocReg CRn, Reg t, size_t coproc_no, size_t opc2, CoprocReg CRm);
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bool thumb32_MRC(bool two, size_t opc1, CoprocReg CRn, Reg t, size_t coproc_no, size_t opc2, CoprocReg CRm);
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// Floating-point three-register data processing instructions
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bool vfp_VADD(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm);
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bool vfp_VSUB(Cond cond, bool D, size_t Vn, size_t Vd, bool sz, bool N, bool M, size_t Vm);
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@ -200,6 +200,9 @@ std::vector<u16> GenRandomThumbInst(u32 pc, bool is_last_inst, A32::ITState it_s
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"vfp_VCVT_from_fixed",
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"asimd_VRECPS", // Unicorn does not fuse the multiply and subtraction, resulting in being off by 1ULP.
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"asimd_VRSQRTS", // Unicorn does not fuse the multiply and subtraction, resulting in being off by 1ULP.
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// Coprocessor
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"thumb32_CDP", "thumb32_LDC", "thumb32_MCR", "thumb32_MCRR", "thumb32_MRC", "thumb32_MRRC", "thumb32_STC",
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};
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for (const auto& [fn, bitstring] : list) {
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