mirrors/dynarmic
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

simd_scalar_two_register_misc: Handle 64-bit case in SCVTF and UCVTF's scalar double/single-precision variant

Browse source 
Avoids falling back to the interpreter in the 64-bit case.
This commit is contained in:
Lioncash 2018-07-09 17:25:13 -04:00 committed by MerryMage
parent 7252293184
commit b97358075e
1 changed files with 2 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp
View file

@ -40,7 +40,7 @@ bool TranslatorVisitor::SCVTF_int_2(bool sz, Vec Vn, Vec Vd) {
if (esize == 32) {
element = ir.FPS32ToSingle(element, false, true);
} else {
return InterpretThisInstruction();
element = ir.FPS64ToDouble(element, false, true);
}
V_scalar(esize, Vd, element);
return true;
@ -53,7 +53,7 @@ bool TranslatorVisitor::UCVTF_int_2(bool sz, Vec Vn, Vec Vd) {
if (esize == 32) {
element = ir.FPU32ToSingle(element, false, true);
} else {
return InterpretThisInstruction();
element = ir.FPU64ToDouble(element, false, true);
}
V_scalar(esize, Vd, element);
return true;