Merge pull request #498 from lioncash/ahp
A32/location_descriptor: Add AHP bit to the FPSCR mask
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commit
bab4e29075
2 changed files with 7 additions and 6 deletions
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@ -135,17 +135,18 @@ void A32JitState::ResetRSB() {
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*
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*
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* SSE MXCSR mode bits
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* SSE MXCSR mode bits
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* -------------------
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* -------------------
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* FZ bit 15 Flush To Zero
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* FZ bit 15 Flush To Zero
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* DAZ bit 6 Denormals Are Zero
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* DAZ bit 6 Denormals Are Zero
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* RN bits 13-14 Round to {0 = Nearest, 1 = Negative, 2 = Positive, 3 = Zero}
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* RN bits 13-14 Round to {0 = Nearest, 1 = Negative, 2 = Positive, 3 = Zero}
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*
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*
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* VFP FPSCR mode bits
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* VFP FPSCR mode bits
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* -------------------
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* -------------------
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* DN bit 25 Default NaN
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* AHP bit 26 Alternate half-precision
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* FZ bit 24 Flush to Zero
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* DN bit 25 Default NaN
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* FZ bit 24 Flush to Zero
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* RMode bits 22-23 Round to {0 = Nearest, 1 = Positive, 2 = Negative, 3 = Zero}
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* RMode bits 22-23 Round to {0 = Nearest, 1 = Positive, 2 = Negative, 3 = Zero}
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* Stride bits 20-21 Vector stride
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* Stride bits 20-21 Vector stride
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* Len bits 16-18 Vector length
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* Len bits 16-18 Vector length
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*/
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*/
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// NZCV; QC (ASMID only), AHP; DN, FZ, RMode, Stride; SBZP; Len; trap enables; cumulative bits
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// NZCV; QC (ASMID only), AHP; DN, FZ, RMode, Stride; SBZP; Len; trap enables; cumulative bits
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@ -26,7 +26,7 @@ class LocationDescriptor {
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public:
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public:
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// Indicates bits that should be preserved within descriptors.
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// Indicates bits that should be preserved within descriptors.
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static constexpr u32 CPSR_MODE_MASK = 0x00000220;
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static constexpr u32 CPSR_MODE_MASK = 0x00000220;
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static constexpr u32 FPSCR_MODE_MASK = 0x03F79F00;
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static constexpr u32 FPSCR_MODE_MASK = 0x07F79F00;
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LocationDescriptor(u32 arm_pc, PSR cpsr, FPSCR fpscr)
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LocationDescriptor(u32 arm_pc, PSR cpsr, FPSCR fpscr)
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: arm_pc(arm_pc), cpsr(cpsr.Value() & CPSR_MODE_MASK), fpscr(fpscr.Value() & FPSCR_MODE_MASK) {}
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: arm_pc(arm_pc), cpsr(cpsr.Value() & CPSR_MODE_MASK), fpscr(fpscr.Value() & FPSCR_MODE_MASK) {}
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