A64: Implement SMADDL, SMSUBL, UMADDL, and UMSUBL

This commit is contained in:
Lioncash 2018-01-23 10:24:53 -05:00 committed by MerryMage
parent c1a25bfc2f
commit bb1c5bd3b2
2 changed files with 48 additions and 4 deletions

View file

@ -339,11 +339,11 @@ INST(CSNEG, "CSNEG", "z1011
// Data Processing - Register - 3 source
INST(MADD, "MADD", "z0011011000mmmmm0aaaaannnnnddddd")
INST(MSUB, "MSUB", "z0011011000mmmmm1aaaaannnnnddddd")
//INST(SMADDL, "SMADDL", "10011011001mmmmm0aaaaannnnnddddd")
//INST(SMSUBL, "SMSUBL", "10011011001mmmmm1aaaaannnnnddddd")
INST(SMADDL, "SMADDL", "10011011001mmmmm0aaaaannnnnddddd")
INST(SMSUBL, "SMSUBL", "10011011001mmmmm1aaaaannnnnddddd")
//INST(SMULH, "SMULH", "10011011010mmmmm011111nnnnnddddd")
//INST(UMADDL, "UMADDL", "10011011101mmmmm0aaaaannnnnddddd")
//INST(UMSUBL, "UMSUBL", "10011011101mmmmm1aaaaannnnnddddd")
INST(UMADDL, "UMADDL", "10011011101mmmmm0aaaaannnnnddddd")
INST(UMSUBL, "UMSUBL", "10011011101mmmmm1aaaaannnnnddddd")
//INST(UMULH, "UMULH", "10011011110mmmmm011111nnnnnddddd")
// Data Processing - FP and SIMD - AES

View file

@ -35,5 +35,49 @@ bool TranslatorVisitor::MSUB(bool sf, Reg Rm, Reg Ra, Reg Rn, Reg Rd) {
return true;
}
bool TranslatorVisitor::SMADDL(Reg Rm, Reg Ra, Reg Rn, Reg Rd) {
const IR::U64 a = X(64, Ra);
const IR::U64 m = ir.SignExtendToLong(X(32, Rm));
const IR::U64 n = ir.SignExtendToLong(X(32, Rn));
const IR::U64 result = ir.Add(a, ir.Mul(n, m));
X(64, Rd, result);
return true;
}
bool TranslatorVisitor::SMSUBL(Reg Rm, Reg Ra, Reg Rn, Reg Rd) {
const IR::U64 a = X(64, Ra);
const IR::U64 m = ir.SignExtendToLong(X(32, Rm));
const IR::U64 n = ir.SignExtendToLong(X(32, Rn));
const IR::U64 result = ir.Sub(a, ir.Mul(n, m));
X(64, Rd, result);
return true;
}
bool TranslatorVisitor::UMADDL(Reg Rm, Reg Ra, Reg Rn, Reg Rd) {
const IR::U64 a = X(64, Ra);
const IR::U64 m = ir.ZeroExtendToLong(X(32, Rm));
const IR::U64 n = ir.ZeroExtendToLong(X(32, Rn));
const IR::U64 result = ir.Add(a, ir.Mul(n, m));
X(64, Rd, result);
return true;
}
bool TranslatorVisitor::UMSUBL(Reg Rm, Reg Ra, Reg Rn, Reg Rd) {
const IR::U64 a = X(64, Ra);
const IR::U64 m = ir.ZeroExtendToLong(X(32, Rm));
const IR::U64 n = ir.ZeroExtendToLong(X(32, Rn));
const IR::U64 result = ir.Sub(a, ir.Mul(n, m));
X(64, Rd, result);
return true;
}
} // namespace A64
} // namespace Dynarmic