mirrors/dynarmic
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

A64: Implement SQABS' vector variant.

Browse source
This commit is contained in:
Lioncash 2018-09-04 22:54:20 -04:00 committed by MerryMage
parent 0507e47420
commit bda5d14c7f
2 changed files with 16 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/frontend/A64/decoder/a64.inc
View file

@ -573,7 +573,7 @@ INST(SADDLP, "SADDLP", "0Q001
//INST(CLS_asimd, "CLS (vector)", "0Q001110zz100000010010nnnnnddddd")
INST(CNT, "CNT", "0Q001110zz100000010110nnnnnddddd")
INST(SADALP, "SADALP", "0Q001110zz100000011010nnnnnddddd")
//INST(SQABS_2, "SQABS", "0Q001110zz100000011110nnnnnddddd")
INST(SQABS_2, "SQABS", "0Q001110zz100000011110nnnnnddddd")
INST(CMGT_zero_2, "CMGT (zero)", "0Q001110zz100000100010nnnnnddddd")
INST(CMEQ_zero_2, "CMEQ (zero)", "0Q001110zz100000100110nnnnnddddd")
INST(CMLT_2, "CMLT (zero)", "0Q001110zz100000101010nnnnnddddd")

15
src/frontend/A64/translate/impl/simd_two_register_misc.cpp
View file

@ -599,6 +599,21 @@ bool TranslatorVisitor::REV64_asimd(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
return true;
}
bool TranslatorVisitor::SQABS_2(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
if (size == 0b11 && !Q) {
return ReservedValue();
}
const size_t esize = 8 << size.ZeroExtend();
const size_t datasize = Q ? 128 : 64;
const IR::U128 operand = V(datasize, Vn);
const IR::U128 result = ir.VectorSignedSaturatedAbs(esize, operand);
V(datasize, Vd, result);
return true;
}
bool TranslatorVisitor::SADALP(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
return PairedAddLong(*this, Q, size, Vn, Vd, Signedness::Signed, PairedAddLongExtraBehavior::Accumulate);
}