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A64: Implement FCVTN{2}

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Lioncash 2018-08-13 22:44:33 -04:00 committed by MerryMage
parent 4c3d7c5a8d
commit be53e356a2
2 changed files with 20 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -580,7 +580,7 @@ INST(CMLT_2, "CMLT (zero)", "0Q001
INST(ABS_2, "ABS", "0Q001110zz100000101110nnnnnddddd")
INST(XTN, "XTN, XTN2", "0Q001110zz100001001010nnnnnddddd")
INST(SQXTN_2, "SQXTN, SQXTN2", "0Q001110zz100001010010nnnnnddddd")
//INST(FCVTN, "FCVTN, FCVTN2", "0Q0011100z100001011010nnnnnddddd")
INST(FCVTN, "FCVTN, FCVTN2", "0Q0011100z100001011010nnnnnddddd")
INST(FCVTL, "FCVTL, FCVTL2", "0Q0011100z100001011110nnnnnddddd")
//INST(FRINTN_1, "FRINTN (vector)", "0Q00111001111001100010nnnnnddddd")
INST(FRINTN_2, "FRINTN (vector)", "0Q0011100z100001100010nnnnnddddd")

19
src/frontend/A64/translate/impl/simd_two_register_misc.cpp
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@ -286,6 +286,25 @@ bool TranslatorVisitor::FCVTL(bool Q, bool sz, Vec Vn, Vec Vd) {
return true;
}
bool TranslatorVisitor::FCVTN(bool Q, bool sz, Vec Vn, Vec Vd) {
// Half-precision not handled directly.
if (!sz) {
return InterpretThisInstruction();
}
const IR::U128 operand = V(128, Vn);
IR::U128 result = ir.ZeroVector();
for (size_t i = 0; i < 2; i++) {
const IR::U32 element = ir.FPDoubleToSingle(ir.VectorGetElement(64, operand, i), true);
result = ir.VectorSetElement(32, result, i, element);
}
Vpart(64, Vd, Q, result);
return true;
}
bool TranslatorVisitor::FCVTNS_4(bool Q, bool sz, Vec Vn, Vec Vd) {
return FloatConvertToInteger(*this, Q, sz, Vn, Vd, Signedness::Signed, FP::RoundingMode::ToNearest_TieEven);
}