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A64: Implement DSB, DMB

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This commit is contained in:
MerryMage 2018-02-11 23:27:28 +00:00
parent 5edd623b9d
commit bfd65bedfe
7 changed files with 34 additions and 2 deletions
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8
src/backend_x64/a64_emit_x64.cpp
View file

@ -316,6 +316,14 @@ void A64EmitX64::EmitA64DataCacheOperationRaised(A64EmitContext& ctx, IR::Inst*
DEVIRT(conf.callbacks, &A64::UserCallbacks::DataCacheOperationRaised).EmitCall(code);
}
void A64EmitX64::EmitA64DataSynchronizationBarrier(A64EmitContext&, IR::Inst*) {
code.mfence();
}
void A64EmitX64::EmitA64DataMemoryBarrier(A64EmitContext&, IR::Inst*) {
code.lfence();
}
void A64EmitX64::EmitA64ReadMemory8(A64EmitContext& ctx, IR::Inst* inst) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
ctx.reg_alloc.HostCall(inst, {}, args[0]);

4
src/frontend/A64/decoder/a64.inc
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@ -62,8 +62,8 @@ INST(SEVL, "SEVL", "11010
//INST(ESB, "ESB", "11010101000000110010001000011111")
//INST(PSB, "PSB CSYNC", "11010101000000110010001000111111")
//INST(CLREX, "CLREX", "11010101000000110011MMMM01011111")
//INST(DSB, "DSB", "11010101000000110011MMMM10011111")
//INST(DMB, "DMB", "11010101000000110011MMMM10111111")
INST(DSB, "DSB", "11010101000000110011MMMM10011111")
INST(DMB, "DMB", "11010101000000110011MMMM10111111")
//INST(ISB, "ISB", "11010101000000110011MMMM11011111")
//INST(SYS, "SYS", "1101010100001oooNNNNMMMMooottttt")
//INST(MSR_reg, "MSR (register)", "110101010001poooNNNNMMMMooottttt")

8
src/frontend/A64/ir_emitter.cpp
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@ -45,6 +45,14 @@ void IREmitter::DataCacheOperationRaised(DataCacheOperation op, const IR::U64& v
Inst(Opcode::A64DataCacheOperationRaised, Imm64(static_cast<u64>(op)), value);
}
void IREmitter::DataSynchronizationBarrier() {
Inst(Opcode::A64DataSynchronizationBarrier);
}
void IREmitter::DataMemoryBarrier() {
Inst(Opcode::A64DataMemoryBarrier);
}
IR::U8 IREmitter::ReadMemory8(const IR::U64& vaddr) {
return Inst<IR::U8>(Opcode::A64ReadMemory8, vaddr);
}

2
src/frontend/A64/ir_emitter.h
View file

@ -42,6 +42,8 @@ public:
void CallSupervisor(u32 imm);
void ExceptionRaised(Exception exception);
void DataCacheOperationRaised(DataCacheOperation op, const IR::U64& value);
void DataSynchronizationBarrier();
void DataMemoryBarrier();
IR::U8 ReadMemory8(const IR::U64& vaddr);
IR::U16 ReadMemory16(const IR::U64& vaddr);

10
src/frontend/A64/translate/impl/system.cpp
View file

@ -36,4 +36,14 @@ bool TranslatorVisitor::SEVL() {
return true;
}
bool TranslatorVisitor::DSB(Imm<4> /*CRm*/) {
ir.DataSynchronizationBarrier();
return true;
}
bool TranslatorVisitor::DMB(Imm<4> /*CRm*/) {
ir.DataMemoryBarrier();
return true;
}
} // namespace Dynarmic::A64

2
src/frontend/ir/microinstruction.cpp
View file

@ -272,6 +272,8 @@ bool Inst::MayHaveSideEffects() const {
return op == Opcode::PushRSB ||
op == Opcode::A64SetCheckBit ||
op == Opcode::A64DataCacheOperationRaised ||
op == Opcode::A64DataSynchronizationBarrier ||
op == Opcode::A64DataMemoryBarrier ||
CausesCPUException() ||
WritesToCoreRegister() ||
WritesToCPSR() ||

2
src/frontend/ir/opcodes.inc
View file

@ -59,6 +59,8 @@ A64OPC(SetPC, T::Void, T::U64
A64OPC(CallSupervisor, T::Void, T::U32 )
A64OPC(ExceptionRaised, T::Void, T::U64, T::U64 )
A64OPC(DataCacheOperationRaised, T::Void, T::U64, T::U64 )
A64OPC(DataSynchronizationBarrier, T::Void, )
A64OPC(DataMemoryBarrier, T::Void, )
// Hints
OPCODE(PushRSB, T::Void, T::U64 )