translate_arm/saturated: Invert conditionals where applicable
This commit is contained in:
Lioncash
MerryMage
parent
a72813599a
commit
c6aa1a708a
1 changed files with 189 additions and 145 deletions
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@ -18,224 +18,268 @@ static IR::U16 MostSignificantHalf(A32::IREmitter& ir, IR::U32 value) {
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// Saturation instructions
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// SSAT<c> <Rd>, #<imm>, <Rn>{, <shift>}
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bool ArmTranslatorVisitor::arm_SSAT(Cond cond, Imm5 sat_imm, Reg d, Imm5 imm5, bool sh, Reg n) {
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if (d == Reg::PC || n == Reg::PC)
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if (d == Reg::PC || n == Reg::PC) {
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return UnpredictableInstruction();
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size_t saturate_to = static_cast<size_t>(sat_imm) + 1;
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ShiftType shift = !sh ? ShiftType::LSL : ShiftType::ASR;
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// SSAT <Rd>, #<saturate_to>, <Rn>
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if (ConditionPassed(cond)) {
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auto operand = EmitImmShift(ir.GetRegister(n), shift, imm5, ir.GetCFlag());
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auto result = ir.SignedSaturation(operand.result, saturate_to);
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ir.SetRegister(d, result.result);
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ir.OrQFlag(result.overflow);
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}
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if (!ConditionPassed(cond)) {
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return true;
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}
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const auto saturate_to = static_cast<size_t>(sat_imm) + 1;
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const auto shift = !sh ? ShiftType::LSL : ShiftType::ASR;
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const auto operand = EmitImmShift(ir.GetRegister(n), shift, imm5, ir.GetCFlag());
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const auto result = ir.SignedSaturation(operand.result, saturate_to);
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ir.SetRegister(d, result.result);
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ir.OrQFlag(result.overflow);
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return true;
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}
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// SSAT16<c> <Rd>, #<imm>, <Rn>
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bool ArmTranslatorVisitor::arm_SSAT16(Cond cond, Imm4 sat_imm, Reg d, Reg n) {
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if (d == Reg::PC || n == Reg::PC)
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if (d == Reg::PC || n == Reg::PC) {
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return UnpredictableInstruction();
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size_t saturate_to = static_cast<size_t>(sat_imm) + 1;
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// SSAT16 <Rd>, #<saturate_to>, <Rn>
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if (ConditionPassed(cond)) {
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auto lo_operand = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(ir.GetRegister(n)));
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auto hi_operand = ir.SignExtendHalfToWord(MostSignificantHalf(ir, ir.GetRegister(n)));
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auto lo_result = ir.SignedSaturation(lo_operand, saturate_to);
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auto hi_result = ir.SignedSaturation(hi_operand, saturate_to);
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ir.SetRegister(d, Pack2x16To1x32(ir, lo_result.result, hi_result.result));
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ir.OrQFlag(lo_result.overflow);
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ir.OrQFlag(hi_result.overflow);
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}
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if (!ConditionPassed(cond)) {
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return true;
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}
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const auto saturate_to = static_cast<size_t>(sat_imm) + 1;
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const auto lo_operand = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(ir.GetRegister(n)));
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const auto hi_operand = ir.SignExtendHalfToWord(MostSignificantHalf(ir, ir.GetRegister(n)));
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const auto lo_result = ir.SignedSaturation(lo_operand, saturate_to);
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const auto hi_result = ir.SignedSaturation(hi_operand, saturate_to);
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ir.SetRegister(d, Pack2x16To1x32(ir, lo_result.result, hi_result.result));
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ir.OrQFlag(lo_result.overflow);
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ir.OrQFlag(hi_result.overflow);
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return true;
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}
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// USAT<c> <Rd>, #<imm5>, <Rn>{, <shift>}
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bool ArmTranslatorVisitor::arm_USAT(Cond cond, Imm5 sat_imm, Reg d, Imm5 imm5, bool sh, Reg n) {
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if (d == Reg::PC || n == Reg::PC)
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if (d == Reg::PC || n == Reg::PC) {
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return UnpredictableInstruction();
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}
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size_t saturate_to = static_cast<size_t>(sat_imm);
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ShiftType shift = !sh ? ShiftType::LSL : ShiftType::ASR;
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if (!ConditionPassed(cond)) {
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return true;
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}
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const auto saturate_to = static_cast<size_t>(sat_imm);
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const auto shift = !sh ? ShiftType::LSL : ShiftType::ASR;
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const auto operand = EmitImmShift(ir.GetRegister(n), shift, imm5, ir.GetCFlag());
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const auto result = ir.UnsignedSaturation(operand.result, saturate_to);
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// USAT <Rd>, #<saturate_to>, <Rn>
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if (ConditionPassed(cond)) {
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auto operand = EmitImmShift(ir.GetRegister(n), shift, imm5, ir.GetCFlag());
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auto result = ir.UnsignedSaturation(operand.result, saturate_to);
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ir.SetRegister(d, result.result);
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ir.OrQFlag(result.overflow);
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}
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return true;
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}
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// USAT16<c> <Rd>, #<imm4>, <Rn>
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bool ArmTranslatorVisitor::arm_USAT16(Cond cond, Imm4 sat_imm, Reg d, Reg n) {
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if (d == Reg::PC || n == Reg::PC)
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if (d == Reg::PC || n == Reg::PC) {
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return UnpredictableInstruction();
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}
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size_t saturate_to = static_cast<size_t>(sat_imm);
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if (!ConditionPassed(cond)) {
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return true;
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}
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// USAT16 <Rd>, #<saturate_to>, <Rn>
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if (ConditionPassed(cond)) {
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// UnsignedSaturation takes a *signed* value as input, hence sign extension is required.
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auto lo_operand = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(ir.GetRegister(n)));
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auto hi_operand = ir.SignExtendHalfToWord(MostSignificantHalf(ir, ir.GetRegister(n)));
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auto lo_result = ir.UnsignedSaturation(lo_operand, saturate_to);
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auto hi_result = ir.UnsignedSaturation(hi_operand, saturate_to);
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const auto saturate_to = static_cast<size_t>(sat_imm);
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const auto lo_operand = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(ir.GetRegister(n)));
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const auto hi_operand = ir.SignExtendHalfToWord(MostSignificantHalf(ir, ir.GetRegister(n)));
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const auto lo_result = ir.UnsignedSaturation(lo_operand, saturate_to);
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const auto hi_result = ir.UnsignedSaturation(hi_operand, saturate_to);
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ir.SetRegister(d, Pack2x16To1x32(ir, lo_result.result, hi_result.result));
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ir.OrQFlag(lo_result.overflow);
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ir.OrQFlag(hi_result.overflow);
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}
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return true;
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}
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// Saturated Add/Subtract instructions
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// QADD<c> <Rd>, <Rm>, <Rn>
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bool ArmTranslatorVisitor::arm_QADD(Cond cond, Reg n, Reg d, Reg m) {
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC) {
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return UnpredictableInstruction();
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// QADD <Rd>, <Rm>, <Rn>
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if (ConditionPassed(cond)) {
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auto a = ir.GetRegister(m);
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auto b = ir.GetRegister(n);
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auto result = ir.SignedSaturatedAdd(a, b);
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ir.SetRegister(d, result.result);
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ir.OrQFlag(result.overflow);
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}
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if (!ConditionPassed(cond)) {
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return true;
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}
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const auto a = ir.GetRegister(m);
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const auto b = ir.GetRegister(n);
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const auto result = ir.SignedSaturatedAdd(a, b);
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ir.SetRegister(d, result.result);
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ir.OrQFlag(result.overflow);
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return true;
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}
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// QSUB<c> <Rd>, <Rm>, <Rn>
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bool ArmTranslatorVisitor::arm_QSUB(Cond cond, Reg n, Reg d, Reg m) {
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC) {
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return UnpredictableInstruction();
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// QSUB <Rd>, <Rm>, <Rn>
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if (ConditionPassed(cond)) {
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auto a = ir.GetRegister(m);
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auto b = ir.GetRegister(n);
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auto result = ir.SignedSaturatedSub(a, b);
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ir.SetRegister(d, result.result);
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ir.OrQFlag(result.overflow);
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}
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if (!ConditionPassed(cond)) {
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return true;
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}
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const auto a = ir.GetRegister(m);
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const auto b = ir.GetRegister(n);
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const auto result = ir.SignedSaturatedSub(a, b);
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ir.SetRegister(d, result.result);
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ir.OrQFlag(result.overflow);
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return true;
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}
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// QDADD<c> <Rd>, <Rm>, <Rn>
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bool ArmTranslatorVisitor::arm_QDADD(Cond cond, Reg n, Reg d, Reg m) {
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC) {
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return UnpredictableInstruction();
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// QDADD <Rd>, <Rm>, <Rn>
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if (ConditionPassed(cond)) {
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auto a = ir.GetRegister(m);
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auto b = ir.GetRegister(n);
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auto doubled = ir.SignedSaturatedAdd(b, b);
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ir.OrQFlag(doubled.overflow);
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auto result = ir.SignedSaturatedAdd(a, doubled.result);
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ir.SetRegister(d, result.result);
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ir.OrQFlag(result.overflow);
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}
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if (!ConditionPassed(cond)) {
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return true;
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}
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bool ArmTranslatorVisitor::arm_QDSUB(Cond cond, Reg n, Reg d, Reg m) {
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
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return UnpredictableInstruction();
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// QDSUB <Rd>, <Rm>, <Rn>
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if (ConditionPassed(cond)) {
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auto a = ir.GetRegister(m);
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auto b = ir.GetRegister(n);
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auto doubled = ir.SignedSaturatedAdd(b, b);
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const auto a = ir.GetRegister(m);
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const auto b = ir.GetRegister(n);
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const auto doubled = ir.SignedSaturatedAdd(b, b);
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ir.OrQFlag(doubled.overflow);
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auto result = ir.SignedSaturatedSub(a, doubled.result);
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const auto result = ir.SignedSaturatedAdd(a, doubled.result);
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ir.SetRegister(d, result.result);
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ir.OrQFlag(result.overflow);
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return true;
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}
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// QDSUB<c> <Rd>, <Rm>, <Rn>
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bool ArmTranslatorVisitor::arm_QDSUB(Cond cond, Reg n, Reg d, Reg m) {
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC) {
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return UnpredictableInstruction();
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}
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if (!ConditionPassed(cond)) {
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return true;
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}
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const auto a = ir.GetRegister(m);
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const auto b = ir.GetRegister(n);
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const auto doubled = ir.SignedSaturatedAdd(b, b);
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ir.OrQFlag(doubled.overflow);
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const auto result = ir.SignedSaturatedSub(a, doubled.result);
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ir.SetRegister(d, result.result);
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ir.OrQFlag(result.overflow);
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return true;
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}
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// Parallel saturated instructions
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// QASX<c> <Rd>, <Rn>, <Rm>
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bool ArmTranslatorVisitor::arm_QASX(Cond cond, Reg n, Reg d, Reg m) {
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC) {
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return UnpredictableInstruction();
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// QASX <Rd>, <Rn>, <Rm>
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if (ConditionPassed(cond)) {
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auto Rn = ir.GetRegister(n);
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auto Rm = ir.GetRegister(m);
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auto Rn_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(Rn));
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auto Rn_hi = ir.SignExtendHalfToWord(MostSignificantHalf(ir, Rn));
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auto Rm_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(Rm));
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auto Rm_hi = ir.SignExtendHalfToWord(MostSignificantHalf(ir, Rm));
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auto diff = ir.SignedSaturation(ir.Sub(Rn_lo, Rm_hi), 16).result;
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auto sum = ir.SignedSaturation(ir.Add(Rn_hi, Rm_lo), 16).result;
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auto result = Pack2x16To1x32(ir, diff, sum);
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ir.SetRegister(d, result);
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}
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if (!ConditionPassed(cond)) {
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return true;
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}
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const auto Rn = ir.GetRegister(n);
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const auto Rm = ir.GetRegister(m);
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const auto Rn_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(Rn));
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const auto Rn_hi = ir.SignExtendHalfToWord(MostSignificantHalf(ir, Rn));
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const auto Rm_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(Rm));
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const auto Rm_hi = ir.SignExtendHalfToWord(MostSignificantHalf(ir, Rm));
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const auto diff = ir.SignedSaturation(ir.Sub(Rn_lo, Rm_hi), 16).result;
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const auto sum = ir.SignedSaturation(ir.Add(Rn_hi, Rm_lo), 16).result;
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const auto result = Pack2x16To1x32(ir, diff, sum);
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ir.SetRegister(d, result);
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return true;
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}
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// QSAX<c> <Rd>, <Rn>, <Rm>
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bool ArmTranslatorVisitor::arm_QSAX(Cond cond, Reg n, Reg d, Reg m) {
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC) {
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return UnpredictableInstruction();
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// QSAX <Rd>, <Rn>, <Rm>
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if (ConditionPassed(cond)) {
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auto Rn = ir.GetRegister(n);
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auto Rm = ir.GetRegister(m);
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auto Rn_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(Rn));
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auto Rn_hi = ir.SignExtendHalfToWord(MostSignificantHalf(ir, Rn));
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auto Rm_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(Rm));
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auto Rm_hi = ir.SignExtendHalfToWord(MostSignificantHalf(ir, Rm));
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auto sum = ir.SignedSaturation(ir.Add(Rn_lo, Rm_hi), 16).result;
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auto diff = ir.SignedSaturation(ir.Sub(Rn_hi, Rm_lo), 16).result;
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auto result = Pack2x16To1x32(ir, sum, diff);
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ir.SetRegister(d, result);
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}
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if (!ConditionPassed(cond)) {
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return true;
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}
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const auto Rn = ir.GetRegister(n);
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const auto Rm = ir.GetRegister(m);
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const auto Rn_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(Rn));
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const auto Rn_hi = ir.SignExtendHalfToWord(MostSignificantHalf(ir, Rn));
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const auto Rm_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(Rm));
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const auto Rm_hi = ir.SignExtendHalfToWord(MostSignificantHalf(ir, Rm));
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const auto sum = ir.SignedSaturation(ir.Add(Rn_lo, Rm_hi), 16).result;
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const auto diff = ir.SignedSaturation(ir.Sub(Rn_hi, Rm_lo), 16).result;
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const auto result = Pack2x16To1x32(ir, sum, diff);
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ir.SetRegister(d, result);
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return true;
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}
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// UQASX<c> <Rd>, <Rn>, <Rm>
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bool ArmTranslatorVisitor::arm_UQASX(Cond cond, Reg n, Reg d, Reg m) {
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC) {
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return UnpredictableInstruction();
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// UQASX <Rd>, <Rn>, <Rm>
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if (ConditionPassed(cond)) {
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auto Rn = ir.GetRegister(n);
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auto Rm = ir.GetRegister(m);
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auto Rn_lo = ir.ZeroExtendHalfToWord(ir.LeastSignificantHalf(Rn));
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auto Rn_hi = ir.ZeroExtendHalfToWord(MostSignificantHalf(ir, Rn));
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auto Rm_lo = ir.ZeroExtendHalfToWord(ir.LeastSignificantHalf(Rm));
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auto Rm_hi = ir.ZeroExtendHalfToWord(MostSignificantHalf(ir, Rm));
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auto diff = ir.UnsignedSaturation(ir.Sub(Rn_lo, Rm_hi), 16).result;
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auto sum = ir.UnsignedSaturation(ir.Add(Rn_hi, Rm_lo), 16).result;
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auto result = Pack2x16To1x32(ir, diff, sum);
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ir.SetRegister(d, result);
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}
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if (!ConditionPassed(cond)) {
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return true;
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}
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bool ArmTranslatorVisitor::arm_UQSAX(Cond cond, Reg n, Reg d, Reg m) {
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
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return UnpredictableInstruction();
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const auto Rn = ir.GetRegister(n);
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const auto Rm = ir.GetRegister(m);
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const auto Rn_lo = ir.ZeroExtendHalfToWord(ir.LeastSignificantHalf(Rn));
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const auto Rn_hi = ir.ZeroExtendHalfToWord(MostSignificantHalf(ir, Rn));
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const auto Rm_lo = ir.ZeroExtendHalfToWord(ir.LeastSignificantHalf(Rm));
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const auto Rm_hi = ir.ZeroExtendHalfToWord(MostSignificantHalf(ir, Rm));
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const auto diff = ir.UnsignedSaturation(ir.Sub(Rn_lo, Rm_hi), 16).result;
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const auto sum = ir.UnsignedSaturation(ir.Add(Rn_hi, Rm_lo), 16).result;
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const auto result = Pack2x16To1x32(ir, diff, sum);
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// UQSAX <Rd>, <Rn>, <Rm>
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if (ConditionPassed(cond)) {
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auto Rn = ir.GetRegister(n);
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auto Rm = ir.GetRegister(m);
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auto Rn_lo = ir.ZeroExtendHalfToWord(ir.LeastSignificantHalf(Rn));
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auto Rn_hi = ir.ZeroExtendHalfToWord(MostSignificantHalf(ir, Rn));
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auto Rm_lo = ir.ZeroExtendHalfToWord(ir.LeastSignificantHalf(Rm));
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auto Rm_hi = ir.ZeroExtendHalfToWord(MostSignificantHalf(ir, Rm));
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auto sum = ir.UnsignedSaturation(ir.Add(Rn_lo, Rm_hi), 16).result;
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auto diff = ir.UnsignedSaturation(ir.Sub(Rn_hi, Rm_lo), 16).result;
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auto result = Pack2x16To1x32(ir, sum, diff);
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ir.SetRegister(d, result);
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return true;
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}
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// UQSAX<c> <Rd>, <Rn>, <Rm>
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bool ArmTranslatorVisitor::arm_UQSAX(Cond cond, Reg n, Reg d, Reg m) {
|
||||
if (d == Reg::PC || n == Reg::PC || m == Reg::PC) {
|
||||
return UnpredictableInstruction();
|
||||
}
|
||||
|
||||
if (!ConditionPassed(cond)) {
|
||||
return true;
|
||||
}
|
||||
|
||||
const auto Rn = ir.GetRegister(n);
|
||||
const auto Rm = ir.GetRegister(m);
|
||||
const auto Rn_lo = ir.ZeroExtendHalfToWord(ir.LeastSignificantHalf(Rn));
|
||||
const auto Rn_hi = ir.ZeroExtendHalfToWord(MostSignificantHalf(ir, Rn));
|
||||
const auto Rm_lo = ir.ZeroExtendHalfToWord(ir.LeastSignificantHalf(Rm));
|
||||
const auto Rm_hi = ir.ZeroExtendHalfToWord(MostSignificantHalf(ir, Rm));
|
||||
const auto sum = ir.UnsignedSaturation(ir.Add(Rn_lo, Rm_hi), 16).result;
|
||||
const auto diff = ir.UnsignedSaturation(ir.Sub(Rn_hi, Rm_lo), 16).result;
|
||||
const auto result = Pack2x16To1x32(ir, sum, diff);
|
||||
|
||||
ir.SetRegister(d, result);
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue