IR: Implement VectorSub
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4 changed files with 36 additions and 0 deletions
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@ -687,6 +687,22 @@ void EmitX64::EmitVectorLogicalShiftRight64(EmitContext& ctx, IR::Inst* inst) {
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ctx.reg_alloc.DefineValue(inst, result);
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}
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void EmitX64::EmitVectorSub8(EmitContext& ctx, IR::Inst* inst) {
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EmitVectorOperation(code, ctx, inst, &Xbyak::CodeGenerator::psubb);
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}
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void EmitX64::EmitVectorSub16(EmitContext& ctx, IR::Inst* inst) {
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EmitVectorOperation(code, ctx, inst, &Xbyak::CodeGenerator::psubw);
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}
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void EmitX64::EmitVectorSub32(EmitContext& ctx, IR::Inst* inst) {
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EmitVectorOperation(code, ctx, inst, &Xbyak::CodeGenerator::psubd);
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}
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void EmitX64::EmitVectorSub64(EmitContext& ctx, IR::Inst* inst) {
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EmitVectorOperation(code, ctx, inst, &Xbyak::CodeGenerator::psubq);
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}
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static void EmitVectorZeroExtend(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, int size) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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@ -934,6 +934,21 @@ U128 IREmitter::VectorPairedAdd(size_t esize, const U128& a, const U128& b) {
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return {};
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}
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U128 IREmitter::VectorSub(size_t esize, const U128& a, const U128& b) {
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switch (esize) {
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case 8:
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return Inst<U128>(Opcode::VectorSub8, a, b);
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case 16:
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return Inst<U128>(Opcode::VectorSub16, a, b);
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case 32:
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return Inst<U128>(Opcode::VectorSub32, a, b);
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case 64:
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return Inst<U128>(Opcode::VectorSub64, a, b);
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}
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UNREACHABLE();
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return {};
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}
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U128 IREmitter::VectorZeroExtend(size_t original_esize, const U128& a) {
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switch (original_esize) {
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case 8:
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@ -220,6 +220,7 @@ public:
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U128 VectorOr(const U128& a, const U128& b);
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U128 VectorPairedAdd(size_t esize, const U128& a, const U128& b);
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U128 VectorPairedAddLower(size_t esize, const U128& a, const U128& b);
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U128 VectorSub(size_t esize, const U128& a, const U128& b);
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U128 VectorZeroExtend(size_t original_esize, const U128& a);
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U128 VectorZeroUpper(const U128& a);
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@ -237,6 +237,10 @@ OPCODE(VectorPairedAdd8, T::U128, T::U128, T::U128
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OPCODE(VectorPairedAdd16, T::U128, T::U128, T::U128 )
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OPCODE(VectorPairedAdd32, T::U128, T::U128, T::U128 )
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OPCODE(VectorPairedAdd64, T::U128, T::U128, T::U128 )
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OPCODE(VectorSub8, T::U128, T::U128, T::U128 )
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OPCODE(VectorSub16, T::U128, T::U128, T::U128 )
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OPCODE(VectorSub32, T::U128, T::U128, T::U128 )
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OPCODE(VectorSub64, T::U128, T::U128, T::U128 )
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OPCODE(VectorZeroExtend8, T::U128, T::U128 )
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OPCODE(VectorZeroExtend16, T::U128, T::U128 )
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OPCODE(VectorZeroExtend32, T::U128, T::U128 )
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