Merge pull request #592 from lioncash/dual
thumb32: Implement LDRD/STRD/TBB/TBH
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merry
GitHub
commit
d0372aebaf
4 changed files with 165 additions and 8 deletions
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@ -163,6 +163,7 @@ if ("A32" IN_LIST DYNARMIC_FRONTENDS)
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frontend/A32/translate/impl/thumb32_data_processing_shifted_register.cpp
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frontend/A32/translate/impl/thumb32_load_byte.cpp
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frontend/A32/translate/impl/thumb32_load_halfword.cpp
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frontend/A32/translate/impl/thumb32_load_store_dual.cpp
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frontend/A32/translate/impl/thumb32_load_store_multiple.cpp
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frontend/A32/translate/impl/thumb32_load_word.cpp
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frontend/A32/translate/impl/thumb32_long_multiply.cpp
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@ -13,17 +13,17 @@ INST(thumb32_LDMDB, "LDMDB/LDMEA", "1110100100W1nnnniiiiii
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// Load/Store Dual, Load/Store Exclusive, Table Branch
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//INST(thumb32_STREX, "STREX", "111010000100--------------------")
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//INST(thumb32_LDREX, "LDREX", "111010000101--------------------")
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//INST(thumb32_STRD_imm_1, "STRD (imm)", "11101000-110--------------------")
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//INST(thumb32_STRD_imm_2, "STRD (imm)", "11101001-1-0--------------------")
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//INST(thumb32_LDRD_imm_1, "LDRD (lit)", "11101000-1111111----------------")
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//INST(thumb32_LDRD_imm_2, "LDRD (lit)", "11101001-1-11111----------------")
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//INST(thumb32_LDRD_imm_1, "LDRD (imm)", "11101000-111--------------------")
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//INST(thumb32_LDRD_imm_2, "LDRD (imm)", "11101001-1-1--------------------")
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INST(thumb32_STRD_imm_1, "STRD (imm)", "11101000U110nnnnttttssssiiiiiiii")
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INST(thumb32_STRD_imm_2, "STRD (imm)", "11101001U1W0nnnnttttssssiiiiiiii")
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INST(thumb32_LDRD_lit_1, "LDRD (lit)", "11101000U1111111ttttssssiiiiiiii")
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INST(thumb32_LDRD_lit_2, "LDRD (lit)", "11101001U1W11111ttttssssiiiiiiii")
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INST(thumb32_LDRD_imm_1, "LDRD (imm)", "11101000U111nnnnttttssssiiiiiiii")
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INST(thumb32_LDRD_imm_2, "LDRD (imm)", "11101001U1W1nnnnttttssssiiiiiiii")
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//INST(thumb32_STREXB, "STREXB", "111010001100------------0100----")
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//INST(thumb32_STREXH, "STREXH", "111010001100------------0101----")
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//INST(thumb32_STREXD, "STREXD", "111010001100------------0111----")
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//INST(thumb32_TBB, "TBB", "111010001101------------0000----")
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//INST(thumb32_TBH, "TBH", "111010001101------------0001----")
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INST(thumb32_TBB, "TBB", "111010001101nnnn111100000000mmmm")
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INST(thumb32_TBH, "TBH", "111010001101nnnn111100000001mmmm")
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//INST(thumb32_LDREXB, "LDREXB", "111010001101------------0100----")
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//INST(thumb32_LDREXH, "LDREXH", "111010001101------------0101----")
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//INST(thumb32_LDREXD, "LDREXD", "111010001101------------0111----")
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146
src/frontend/A32/translate/impl/thumb32_load_store_dual.cpp
Normal file
146
src/frontend/A32/translate/impl/thumb32_load_store_dual.cpp
Normal file
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@ -0,0 +1,146 @@
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/* This file is part of the dynarmic project.
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* Copyright (c) 2021 MerryMage
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* SPDX-License-Identifier: 0BSD
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*/
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#include "common/bit_util.h"
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#include "frontend/A32/translate/impl/translate_thumb.h"
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namespace Dynarmic::A32 {
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static bool ITBlockCheck(const A32::IREmitter& ir) {
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return ir.current_location.IT().IsInITBlock() && !ir.current_location.IT().IsLastInITBlock();
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}
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static bool TableBranch(ThumbTranslatorVisitor& v, Reg n, Reg m, bool half) {
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if (m == Reg::PC) {
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return v.UnpredictableInstruction();
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}
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if (ITBlockCheck(v.ir)) {
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return v.UnpredictableInstruction();
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}
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const auto reg_m = v.ir.GetRegister(m);
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const auto reg_n = v.ir.GetRegister(n);
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IR::U32 halfwords;
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if (half) {
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const auto data = v.ir.ReadMemory16(v.ir.Add(reg_n, v.ir.LogicalShiftLeft(reg_m, v.ir.Imm8(1))));
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halfwords = v.ir.ZeroExtendToWord(data);
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} else {
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halfwords = v.ir.ZeroExtendToWord(v.ir.ReadMemory8(v.ir.Add(reg_n, reg_m)));
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}
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const auto current_pc = v.ir.Imm32(v.ir.PC());
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const auto branch_value = v.ir.Add(current_pc, v.ir.Add(halfwords, halfwords));
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v.ir.UpdateUpperLocationDescriptor();
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v.ir.BranchWritePC(branch_value);
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v.ir.SetTerm(IR::Term::FastDispatchHint{});
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return false;
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}
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static bool LoadDualImmediate(ThumbTranslatorVisitor& v, bool P, bool U, bool W,
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Reg n, Reg t, Reg t2, Imm<8> imm8) {
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if (W && (n == t || n == t2)) {
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return v.UnpredictableInstruction();
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}
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if (t == Reg::PC || t2 == Reg::PC || t == t2) {
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return v.UnpredictableInstruction();
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}
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const u32 imm = imm8.ZeroExtend() << 2;
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const IR::U32 reg_n = v.ir.GetRegister(n);
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const IR::U32 offset_address = U ? v.ir.Add(reg_n, v.ir.Imm32(imm))
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: v.ir.Sub(reg_n, v.ir.Imm32(imm));
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const IR::U32 address_1 = P ? offset_address
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: reg_n;
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const IR::U32 address_2 = v.ir.Add(address_1, v.ir.Imm32(4));
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v.ir.SetRegister(t, v.ir.ReadMemory32(address_1));
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v.ir.SetRegister(t2, v.ir.ReadMemory32(address_2));
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if (W) {
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v.ir.SetRegister(n, offset_address);
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}
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return true;
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}
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static bool LoadDualLiteral(ThumbTranslatorVisitor& v, bool U, bool W, Reg t, Reg t2, Imm<8> imm8) {
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if (t == Reg::PC || t2 == Reg::PC || t == t2) {
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return v.UnpredictableInstruction();
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}
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if (W) {
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return v.UnpredictableInstruction();
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}
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const auto imm = imm8.ZeroExtend() << 2;
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const auto address_1 = U ? v.ir.Add(v.ir.Imm32(v.ir.AlignPC(4)), v.ir.Imm32(imm))
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: v.ir.Sub(v.ir.Imm32(v.ir.AlignPC(4)), v.ir.Imm32(imm));
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const auto address_2 = v.ir.Add(address_1, v.ir.Imm32(4));
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v.ir.SetRegister(t, v.ir.ReadMemory32(address_1));
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v.ir.SetRegister(t2, v.ir.ReadMemory32(address_2));
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return true;
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}
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static bool StoreDual(ThumbTranslatorVisitor& v, bool P, bool U, bool W, Reg n, Reg t, Reg t2, Imm<8> imm8) {
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if (W && (n == t || n == t2)) {
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return v.UnpredictableInstruction();
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}
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if (n == Reg::PC || t == Reg::PC || t2 == Reg::PC) {
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return v.UnpredictableInstruction();
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}
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const u32 imm = imm8.ZeroExtend() << 2;
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const IR::U32 reg_n = v.ir.GetRegister(n);
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const IR::U32 reg_t = v.ir.GetRegister(t);
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const IR::U32 reg_t2 = v.ir.GetRegister(t2);
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const IR::U32 offset_address = U ? v.ir.Add(reg_n, v.ir.Imm32(imm))
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: v.ir.Sub(reg_n, v.ir.Imm32(imm));
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const IR::U32 address_1 = P ? offset_address
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: reg_n;
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const IR::U32 address_2 = v.ir.Add(address_1, v.ir.Imm32(4));
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v.ir.WriteMemory32(address_1, reg_t);
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v.ir.WriteMemory32(address_2, reg_t2);
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if (W) {
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v.ir.SetRegister(n, offset_address);
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}
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_LDRD_imm_1(bool U, Reg n, Reg t, Reg t2, Imm<8> imm8) {
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return LoadDualImmediate(*this, false, U, true, n, t, t2, imm8);
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}
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bool ThumbTranslatorVisitor::thumb32_LDRD_imm_2(bool U, bool W, Reg n, Reg t, Reg t2, Imm<8> imm8) {
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return LoadDualImmediate(*this, true, U, W, n, t, t2, imm8);
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}
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bool ThumbTranslatorVisitor::thumb32_LDRD_lit_1(bool U, Reg t, Reg t2, Imm<8> imm8) {
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return LoadDualLiteral(*this, U, true, t, t2, imm8);
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}
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bool ThumbTranslatorVisitor::thumb32_LDRD_lit_2(bool U, bool W, Reg t, Reg t2, Imm<8> imm8) {
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return LoadDualLiteral(*this, U, W, t, t2, imm8);
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}
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bool ThumbTranslatorVisitor::thumb32_STRD_imm_1(bool U, Reg n, Reg t, Reg t2, Imm<8> imm8) {
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return StoreDual(*this, false, U, true, n, t, t2, imm8);
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}
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bool ThumbTranslatorVisitor::thumb32_STRD_imm_2(bool U, bool W, Reg n, Reg t, Reg t2, Imm<8> imm8) {
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return StoreDual(*this, true, U, W, n, t, t2, imm8);
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}
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bool ThumbTranslatorVisitor::thumb32_TBB(Reg n, Reg m) {
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return TableBranch(*this, n, m, false);
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}
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bool ThumbTranslatorVisitor::thumb32_TBH(Reg n, Reg m) {
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return TableBranch(*this, n, m, true);
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}
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} // namespace Dynarmic::A32
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@ -179,6 +179,16 @@ struct ThumbTranslatorVisitor final {
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bool thumb32_STMIA(bool W, Reg n, Imm<15> reg_list);
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bool thumb32_STMDB(bool W, Reg n, Imm<15> reg_list);
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// thumb32 load/store dual, load/store exclusive, table branch instructions
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bool thumb32_LDRD_imm_1(bool U, Reg n, Reg t, Reg t2, Imm<8> imm8);
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bool thumb32_LDRD_imm_2(bool U, bool W, Reg n, Reg t, Reg t2, Imm<8> imm8);
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bool thumb32_LDRD_lit_1(bool U, Reg t, Reg t2, Imm<8> imm8);
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bool thumb32_LDRD_lit_2(bool U, bool W, Reg t, Reg t2, Imm<8> imm8);
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bool thumb32_STRD_imm_1(bool U, Reg n, Reg t, Reg t2, Imm<8> imm8);
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bool thumb32_STRD_imm_2(bool U, bool W, Reg n, Reg t, Reg t2, Imm<8> imm8);
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bool thumb32_TBB(Reg n, Reg m);
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bool thumb32_TBH(Reg n, Reg m);
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// thumb32 data processing (shifted register) instructions
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bool thumb32_TST_reg(Reg n, Imm<3> imm3, Imm<2> imm2, ShiftType type, Reg m);
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bool thumb32_AND_reg(bool S, Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, ShiftType type, Reg m);
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