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A64: Implement INS (element)

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MerryMage 2018-02-03 13:03:50 +00:00
parent 0642d49919
commit d13704fdef
2 changed files with 18 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -675,7 +675,7 @@ INST(DUP_gen, "DUP (general)", "0Q001
INST(SMOV, "SMOV", "0Q001110000iiiii001011nnnnnddddd") INST(SMOV, "SMOV", "0Q001110000iiiii001011nnnnnddddd")
INST(UMOV, "UMOV", "0Q001110000iiiii001111nnnnnddddd") INST(UMOV, "UMOV", "0Q001110000iiiii001111nnnnnddddd")
//INST(INS_gen, "INS (general)", "01001110000iiiii000111nnnnnddddd") //INST(INS_gen, "INS (general)", "01001110000iiiii000111nnnnnddddd")
//INST(INS_elt, "INS (element)", "01101110000iiiii0iiii1nnnnnddddd") INST(INS_elt, "INS (element)", "01101110000iiiii0iiii1nnnnnddddd")
// Data Processing - FP and SIMD - SIMD Three same // Data Processing - FP and SIMD - SIMD Three same
//INST(FMAXNM_1, "FMAXNM (vector)", "0Q001110010mmmmm000001nnnnnddddd") //INST(FMAXNM_1, "FMAXNM (vector)", "0Q001110010mmmmm000001nnnnnddddd")

17
src/frontend/A64/translate/impl/simd_copy.cpp
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@ -73,4 +73,21 @@ bool TranslatorVisitor::UMOV(bool Q, Imm<5> imm5, Vec Vn, Reg Rd) {
return true; return true;
} }
bool TranslatorVisitor::INS_elt(Imm<5> imm5, Imm<4> imm4, Vec Vn, Vec Vd) {
const size_t size = Common::LowestSetBit(imm5.ZeroExtend());
if (size > 3) return UnallocatedEncoding();
const size_t dst_index = imm5.ZeroExtend<size_t>() >> (size + 1);
const size_t src_index = imm4.ZeroExtend<size_t>() >> size;
const size_t idxdsize = imm4.Bit<3>() ? 128 : 64;
const size_t esize = 8 << size;
const IR::U128 operand = V(idxdsize, Vn);
const IR::UAny elem = ir.VectorGetElement(esize, operand, src_index);
const IR::U128 result = ir.VectorSetElement(esize, V(128, Vd), dst_index, elem);
V(128, Vd, result);
return true;
}
} // namespace Dynarmic::A64 } // namespace Dynarmic::A64