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thumb32: Implement SADD16/UADD16

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This commit is contained in:
Lioncash 2021-02-01 16:11:25 -05:00
parent 0e26e8a531
commit d529417875
5 changed files with 61 additions and 32 deletions
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1
src/CMakeLists.txt
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@ -152,6 +152,7 @@ if ("A32" IN_LIST DYNARMIC_FRONTENDS)
frontend/A32/translate/impl/thumb16.cpp frontend/A32/translate/impl/thumb16.cpp
frontend/A32/translate/impl/thumb32.cpp frontend/A32/translate/impl/thumb32.cpp
frontend/A32/translate/impl/thumb32_misc.cpp frontend/A32/translate/impl/thumb32_misc.cpp
frontend/A32/translate/impl/thumb32_parallel.cpp
frontend/A32/translate/impl/translate_arm.h frontend/A32/translate/impl/translate_arm.h
frontend/A32/translate/impl/translate_thumb.h frontend/A32/translate/impl/translate_thumb.h
frontend/A32/translate/impl/vfp.cpp frontend/A32/translate/impl/vfp.cpp

4
src/frontend/A32/decoder/thumb32.h
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@ -235,7 +235,7 @@ std::optional<std::reference_wrapper<const Thumb32Matcher<V>>> DecodeThumb32(u32
//INST(&V::thumb32_UXTAB, "UXTAB", "111110100101----1111----1-------"), //INST(&V::thumb32_UXTAB, "UXTAB", "111110100101----1111----1-------"),
// Parallel Addition and Subtraction (signed) // Parallel Addition and Subtraction (signed)
//INST(&V::thumb32_SADD16, "SADD16", "111110101001----1111----0000----"), INST(&V::thumb32_SADD16, "SADD16", "111110101001nnnn1111dddd0000mmmm"),
//INST(&V::thumb32_SASX, "SASX", "111110101010----1111----0000----"), //INST(&V::thumb32_SASX, "SASX", "111110101010----1111----0000----"),
//INST(&V::thumb32_SSAX, "SSAX", "111110101110----1111----0000----"), //INST(&V::thumb32_SSAX, "SSAX", "111110101110----1111----0000----"),
//INST(&V::thumb32_SSUB16, "SSUB16", "111110101101----1111----0000----"), //INST(&V::thumb32_SSUB16, "SSUB16", "111110101101----1111----0000----"),
@ -255,7 +255,7 @@ std::optional<std::reference_wrapper<const Thumb32Matcher<V>>> DecodeThumb32(u32
//INST(&V::thumb32_SHSUB8, "SHSUB8", "111110101100----1111----0010----"), //INST(&V::thumb32_SHSUB8, "SHSUB8", "111110101100----1111----0010----"),
// Parallel Addition and Subtraction (unsigned) // Parallel Addition and Subtraction (unsigned)
//INST(&V::thumb32_UADD16, "UADD16", "111110101001----1111----0100----"), INST(&V::thumb32_UADD16, "UADD16", "111110101001nnnn1111dddd0100mmmm"),
//INST(&V::thumb32_UASX, "UASX", "111110101010----1111----0100----"), //INST(&V::thumb32_UASX, "UASX", "111110101010----1111----0100----"),
//INST(&V::thumb32_USAX, "USAX", "111110101110----1111----0100----"), //INST(&V::thumb32_USAX, "USAX", "111110101110----1111----0100----"),
//INST(&V::thumb32_USUB16, "USUB16", "111110101101----1111----0100----"), //INST(&V::thumb32_USUB16, "USUB16", "111110101101----1111----0100----"),

38
src/frontend/A32/translate/impl/thumb32_parallel.cpp Normal file
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@ -0,0 +1,38 @@
/* This file is part of the dynarmic project.
* Copyright (c) 2016 MerryMage
* SPDX-License-Identifier: 0BSD
*/
#include "frontend/A32/translate/impl/translate_thumb.h"
namespace Dynarmic::A32 {
bool ThumbTranslatorVisitor::thumb32_SADD16(Reg n, Reg d, Reg m) {
if (d == Reg::PC || n == Reg::PC || m == Reg::PC) {
return UnpredictableInstruction();
}
const auto reg_m = ir.GetRegister(m);
const auto reg_n = ir.GetRegister(n);
const auto result = ir.PackedAddS16(reg_n, reg_m);
ir.SetRegister(d, result.result);
ir.SetGEFlags(result.ge);
return true;
}
bool ThumbTranslatorVisitor::thumb32_UADD16(Reg n, Reg d, Reg m) {
if (d == Reg::PC || n == Reg::PC || m == Reg::PC) {
return UnpredictableInstruction();
}
const auto reg_m = ir.GetRegister(m);
const auto reg_n = ir.GetRegister(n);
const auto result = ir.PackedAddU16(reg_n, reg_m);
ir.SetRegister(d, result.result);
ir.SetGEFlags(result.ge);
return true;
}
} // namespace Dynarmic::A32

4
src/frontend/A32/translate/impl/translate_thumb.h
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@ -127,6 +127,10 @@ struct ThumbTranslatorVisitor final {
bool thumb32_REV16(Reg n, Reg d, Reg m); bool thumb32_REV16(Reg n, Reg d, Reg m);
bool thumb32_REVSH(Reg n, Reg d, Reg m); bool thumb32_REVSH(Reg n, Reg d, Reg m);
bool thumb32_SEL(Reg n, Reg d, Reg m); bool thumb32_SEL(Reg n, Reg d, Reg m);
// thumb32 parallel add/sub instructions
bool thumb32_SADD16(Reg n, Reg d, Reg m);
bool thumb32_UADD16(Reg n, Reg d, Reg m);
}; };
} // namespace Dynarmic::A32 } // namespace Dynarmic::A32

46
tests/A32/fuzz_thumb.cpp
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@ -361,6 +361,13 @@ TEST_CASE("Fuzz Thumb instructions set 2 (affects PC)", "[JitX64][Thumb][Thumb16
} }
TEST_CASE("Fuzz Thumb32 instructions set", "[JitX64][Thumb][Thumb32]") { TEST_CASE("Fuzz Thumb32 instructions set", "[JitX64][Thumb][Thumb32]") {
const auto three_reg_not_r15 = [](u32 inst) {
const auto d = Common::Bits<8, 11>(inst);
const auto m = Common::Bits<0, 3>(inst);
const auto n = Common::Bits<16, 19>(inst);
return d != 15 && m != 15 && n != 15;
};
const std::array instructions = { const std::array instructions = {
ThumbInstGen("111110101011nnnn1111dddd1000mmmm", // CLZ ThumbInstGen("111110101011nnnn1111dddd1000mmmm", // CLZ
[](u32 inst) { [](u32 inst) {
@ -370,33 +377,13 @@ TEST_CASE("Fuzz Thumb32 instructions set", "[JitX64][Thumb][Thumb32]") {
return m == n && d != 15 && m != 15; return m == n && d != 15 && m != 15;
}), }),
ThumbInstGen("111110101000nnnn1111dddd1000mmmm", // QADD ThumbInstGen("111110101000nnnn1111dddd1000mmmm", // QADD
[](u32 inst) { three_reg_not_r15),
const auto d = Common::Bits<8, 11>(inst);
const auto m = Common::Bits<0, 3>(inst);
const auto n = Common::Bits<16, 19>(inst);
return d != 15 && m != 15 && n != 15;
}),
ThumbInstGen("111110101000nnnn1111dddd1001mmmm", // QDADD ThumbInstGen("111110101000nnnn1111dddd1001mmmm", // QDADD
[](u32 inst) { three_reg_not_r15),
const auto d = Common::Bits<8, 11>(inst);
const auto m = Common::Bits<0, 3>(inst);
const auto n = Common::Bits<16, 19>(inst);
return d != 15 && m != 15 && n != 15;
}),
ThumbInstGen("111110101000nnnn1111dddd1011mmmm", // QDSUB ThumbInstGen("111110101000nnnn1111dddd1011mmmm", // QDSUB
[](u32 inst) { three_reg_not_r15),
const auto d = Common::Bits<8, 11>(inst);
const auto m = Common::Bits<0, 3>(inst);
const auto n = Common::Bits<16, 19>(inst);
return d != 15 && m != 15 && n != 15;
}),
ThumbInstGen("111110101000nnnn1111dddd1010mmmm", // QSUB ThumbInstGen("111110101000nnnn1111dddd1010mmmm", // QSUB
[](u32 inst) { three_reg_not_r15),
const auto d = Common::Bits<8, 11>(inst);
const auto m = Common::Bits<0, 3>(inst);
const auto n = Common::Bits<16, 19>(inst);
return d != 15 && m != 15 && n != 15;
}),
ThumbInstGen("111110101001nnnn1111dddd1010mmmm", // RBIT ThumbInstGen("111110101001nnnn1111dddd1010mmmm", // RBIT
[](u32 inst) { [](u32 inst) {
const auto d = Common::Bits<8, 11>(inst); const auto d = Common::Bits<8, 11>(inst);
@ -425,13 +412,12 @@ TEST_CASE("Fuzz Thumb32 instructions set", "[JitX64][Thumb][Thumb32]") {
const auto n = Common::Bits<16, 19>(inst); const auto n = Common::Bits<16, 19>(inst);
return m == n && d != 15 && m != 15; return m == n && d != 15 && m != 15;
}), }),
ThumbInstGen("111110101001nnnn1111dddd0000mmmm", // SADD16
three_reg_not_r15),
ThumbInstGen("111110101010nnnn1111dddd1000mmmm", // SEL ThumbInstGen("111110101010nnnn1111dddd1000mmmm", // SEL
[](u32 inst) { three_reg_not_r15),
const auto d = Common::Bits<8, 11>(inst); ThumbInstGen("111110101001nnnn1111dddd0100mmmm", // UADD16
const auto m = Common::Bits<0, 3>(inst); three_reg_not_r15),
const auto n = Common::Bits<16, 19>(inst);
return d != 15 && m != 15 && n != 15;
}),
}; };
const auto instruction_select = [&]() -> u32 { const auto instruction_select = [&]() -> u32 {