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A32: Implement ASIMD VBSL (register)

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Lioncash 2020-05-16 13:24:18 -04:00 committed by merry
parent 66663cf8e7
commit d624059ead
3 changed files with 29 additions and 1 deletions
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2
src/frontend/A32/decoder/asimd.inc
View file

@ -7,7 +7,7 @@ INST(asimd_VBIC_reg, "VBIC (register)", "111100100D01nnnndddd000
INST(asimd_VORR_reg, "VORR (register)", "111100100D10nnnndddd0001NQM1mmmm") // ASIMD INST(asimd_VORR_reg, "VORR (register)", "111100100D10nnnndddd0001NQM1mmmm") // ASIMD
INST(asimd_VORN_reg, "VORN (register)", "111100100D11nnnndddd0001NQM1mmmm") // ASIMD INST(asimd_VORN_reg, "VORN (register)", "111100100D11nnnndddd0001NQM1mmmm") // ASIMD
INST(asimd_VEOR_reg, "VEOR (register)", "111100110D00nnnndddd0001NQM1mmmm") // ASIMD INST(asimd_VEOR_reg, "VEOR (register)", "111100110D00nnnndddd0001NQM1mmmm") // ASIMD
//INST(asimd_VBSL, "VBSL", "111100110-01--------0001---1----") // ASIMD INST(asimd_VBSL, "VBSL", "111100110D01nnnndddd0001NQM1mmmm") // ASIMD
//INST(asimd_VBIT, "VBIT", "111100110-10--------0001---1----") // ASIMD //INST(asimd_VBIT, "VBIT", "111100110-10--------0001---1----") // ASIMD
//INST(asimd_VBIF, "VBIF", "111100110-11--------0001---1----") // ASIMD //INST(asimd_VBIF, "VBIF", "111100110-11--------0001---1----") // ASIMD
//INST(asimd_VHADD, "VHADD", "1111001U0-CC--------0010---0----") // ASIMD //INST(asimd_VHADD, "VHADD", "1111001U0-CC--------0010---0----") // ASIMD

27
src/frontend/A32/translate/impl/asimd_three_same.cpp
View file

@ -33,6 +33,28 @@ bool BitwiseInstruction(ArmTranslatorVisitor& v, bool D, size_t Vn, size_t Vd, b
return true; return true;
} }
template <typename Callable>
bool BitwiseInstructionWithDst(ArmTranslatorVisitor& v, bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm, Callable fn) {
if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) {
return v.UndefinedInstruction();
}
const auto d = ToExtReg(Vd, D);
const auto m = ToExtReg(Vm, M);
const auto n = ToExtReg(Vn, N);
const size_t regs = Q ? 2 : 1;
for (size_t i = 0; i < regs; i++) {
const IR::U32U64 reg_d = v.ir.GetExtendedRegister(d + i);
const IR::U32U64 reg_m = v.ir.GetExtendedRegister(m + i);
const IR::U32U64 reg_n = v.ir.GetExtendedRegister(n + i);
const IR::U32U64 result = fn(reg_d, reg_n, reg_m);
v.ir.SetExtendedRegister(d + i, result);
}
return true;
}
} // Anonymous namespace } // Anonymous namespace
bool ArmTranslatorVisitor::asimd_VAND_reg(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) { bool ArmTranslatorVisitor::asimd_VAND_reg(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
@ -65,4 +87,9 @@ bool ArmTranslatorVisitor::asimd_VEOR_reg(bool D, size_t Vn, size_t Vd, bool N,
}); });
} }
bool ArmTranslatorVisitor::asimd_VBSL(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
return BitwiseInstructionWithDst(*this, D, Vn, Vd, N, Q, M, Vm, [this](const auto& reg_d, const auto& reg_n, const auto& reg_m) {
return ir.Or(ir.And(reg_n, reg_d), ir.And(reg_m, ir.Not(reg_d)));
});
}
} // namespace Dynarmic::A32 } // namespace Dynarmic::A32

1
src/frontend/A32/translate/impl/translate_arm.h
View file

@ -435,6 +435,7 @@ struct ArmTranslatorVisitor final {
bool asimd_VORR_reg(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm); bool asimd_VORR_reg(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
bool asimd_VORN_reg(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm); bool asimd_VORN_reg(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
bool asimd_VEOR_reg(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm); bool asimd_VEOR_reg(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
bool asimd_VBSL(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
// Advanced SIMD load/store structures // Advanced SIMD load/store structures
bool v8_VLD_multiple(bool D, Reg n, size_t Vd, Imm<4> type, size_t sz, size_t align, Reg m); bool v8_VLD_multiple(bool D, Reg n, size_t Vd, Imm<4> type, size_t sz, size_t align, Reg m);