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A64: Implement FCMEQ (zero)'s vector single and double precision variant

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Lioncash 2018-06-02 16:39:57 -04:00 committed by MerryMage
parent 9bec354791
commit d86fea0d28
2 changed files with 16 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -597,7 +597,7 @@ INST(SCVTF_int_4, "SCVTF (vector, integer)", "0Q001
//INST(FCMGT_zero_3, "FCMGT (zero)", "0Q00111011111000110010nnnnnddddd")
//INST(FCMGT_zero_4, "FCMGT (zero)", "0Q0011101z100000110010nnnnnddddd")
//INST(FCMEQ_zero_3, "FCMEQ (zero)", "0Q00111011111000110110nnnnnddddd")
//INST(FCMEQ_zero_4, "FCMEQ (zero)", "0Q0011101z100000110110nnnnnddddd")
INST(FCMEQ_zero_4, "FCMEQ (zero)", "0Q0011101z100000110110nnnnnddddd")
//INST(FCMLT_3, "FCMLT (zero)", "0Q00111011111000111010nnnnnddddd")
//INST(FCMLT_4, "FCMLT (zero)", "0Q0011101z100000111010nnnnnddddd")
INST(FABS_1, "FABS (vector)", "0Q00111011111000111110nnnnnddddd")

15
src/frontend/A64/translate/impl/simd_two_register_misc.cpp
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@ -142,6 +142,21 @@ bool TranslatorVisitor::FABS_2(bool Q, bool sz, Vec Vn, Vec Vd) {
return true;
}
bool TranslatorVisitor::FCMEQ_zero_4(bool Q, bool sz, Vec Vn, Vec Vd) {
if (sz && !Q) {
return ReservedValue();
}
const size_t esize = sz ? 64 : 32;
const size_t datasize = Q ? 128 : 64;
const IR::U128 operand = V(datasize, Vn);
const IR::U128 result = ir.FPVectorEqual(esize, operand, ir.ZeroVector());
V(datasize, Vd, result);
return true;
}
bool TranslatorVisitor::FNEG_1(bool Q, Vec Vn, Vec Vd) {
const size_t datasize = Q ? 128 : 64;