TranlateArm: implement remaining multiplies
SMLALxy, SMLAxy, SMULxy SMLAWy, SMULWy, SMLAD, SMLALD, SMLSD, SMLSLD, SMUAD, SMUSD
This commit is contained in:
Tillmann Karras
MerryMage
parent
f12578b9ab
commit
dad7724b86
2 changed files with 232 additions and 25 deletions
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@ -147,25 +147,94 @@ bool ArmTranslatorVisitor::arm_UMULL(Cond cond, bool S, Reg dHi, Reg dLo, Reg m,
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// Multiply (Halfword) instructions
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bool ArmTranslatorVisitor::arm_SMLALxy(Cond cond, Reg dHi, Reg dLo, Reg m, bool M, bool N, Reg n) {
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return InterpretThisInstruction();
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if (dLo == Reg::PC || dHi == Reg::PC || n == Reg::PC || m == Reg::PC)
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return UnpredictableInstruction();
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if (dLo == dHi)
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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auto n32 = ir.GetRegister(n);
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auto m32 = ir.GetRegister(m);
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auto n16 = N ? ir.ArithmeticShiftRight(n32, ir.Imm8(16), ir.Imm1(0)).result
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: ir.SignExtendHalfToWord(ir.LeastSignificantHalf(n32));
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auto m16 = M ? ir.ArithmeticShiftRight(m32, ir.Imm8(16), ir.Imm1(0)).result
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: ir.SignExtendHalfToWord(ir.LeastSignificantHalf(m32));
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auto product = ir.SignExtendWordToLong(ir.Mul(n16, m16));
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auto addend = ir.Pack2x32To1x64(ir.GetRegister(dLo), ir.GetRegister(dHi));
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auto result = ir.Add64(product, addend);
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ir.SetRegister(dLo, ir.LeastSignificantWord(result));
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ir.SetRegister(dHi, ir.MostSignificantWord(result).result);
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}
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return true;
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}
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bool ArmTranslatorVisitor::arm_SMLAxy(Cond cond, Reg d, Reg a, Reg m, bool M, bool N, Reg n) {
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return InterpretThisInstruction();
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC || a == Reg::PC)
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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auto n32 = ir.GetRegister(n);
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auto m32 = ir.GetRegister(m);
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auto n16 = N ? ir.ArithmeticShiftRight(n32, ir.Imm8(16), ir.Imm1(0)).result
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: ir.SignExtendHalfToWord(ir.LeastSignificantHalf(n32));
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auto m16 = M ? ir.ArithmeticShiftRight(m32, ir.Imm8(16), ir.Imm1(0)).result
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: ir.SignExtendHalfToWord(ir.LeastSignificantHalf(m32));
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auto product = ir.Mul(n16, m16);
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auto result_overflow = ir.AddWithCarry(product, ir.GetRegister(a), ir.Imm1(0));
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ir.SetRegister(d, result_overflow.result);
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ir.OrQFlag(result_overflow.overflow);
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}
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return true;
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}
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bool ArmTranslatorVisitor::arm_SMULxy(Cond cond, Reg d, Reg m, bool M, bool N, Reg n) {
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return InterpretThisInstruction();
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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auto n32 = ir.GetRegister(n);
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auto m32 = ir.GetRegister(m);
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auto n16 = N ? ir.ArithmeticShiftRight(n32, ir.Imm8(16), ir.Imm1(0)).result
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: ir.SignExtendHalfToWord(ir.LeastSignificantHalf(n32));
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auto m16 = M ? ir.ArithmeticShiftRight(m32, ir.Imm8(16), ir.Imm1(0)).result
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: ir.SignExtendHalfToWord(ir.LeastSignificantHalf(m32));
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auto result = ir.Mul(n16, m16);
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ir.SetRegister(d, result);
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}
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return true;
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}
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// Multiply (word by halfword) instructions
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bool ArmTranslatorVisitor::arm_SMLAWy(Cond cond, Reg d, Reg a, Reg m, bool M, Reg n) {
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return InterpretThisInstruction();
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC || a == Reg::PC)
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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auto n32 = ir.SignExtendWordToLong(ir.GetRegister(n));
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auto m32 = ir.GetRegister(m);
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if (M)
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m32 = ir.LogicalShiftRight(m32, ir.Imm8(16), ir.Imm1(0)).result;
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auto m16 = ir.LeastSignificantHalf(m32);
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m16 = ir.SignExtendWordToLong(ir.SignExtendHalfToWord(m16));
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auto product = ir.LeastSignificantWord(ir.LogicalShiftRight64(ir.Mul64(n32, m16), ir.Imm8(16)));
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auto result_overflow = ir.AddWithCarry(product, ir.GetRegister(a), ir.Imm1(0));
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ir.SetRegister(d, result_overflow.result);
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ir.OrQFlag(result_overflow.overflow);
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}
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return true;
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}
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bool ArmTranslatorVisitor::arm_SMULWy(Cond cond, Reg d, Reg m, bool M, Reg n) {
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return InterpretThisInstruction();
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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auto n32 = ir.SignExtendWordToLong(ir.GetRegister(n));
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auto m32 = ir.GetRegister(m);
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if (M)
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m32 = ir.LogicalShiftRight(m32, ir.Imm8(16), ir.Imm1(0)).result;
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auto m16 = ir.LeastSignificantHalf(m32);
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m16 = ir.SignExtendWordToLong(ir.SignExtendHalfToWord(m16));
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auto result = ir.LogicalShiftRight64(ir.Mul64(n32, m16), ir.Imm8(16));
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ir.SetRegister(d, ir.LeastSignificantWord(result));
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}
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return true;
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}
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@ -223,27 +292,142 @@ bool ArmTranslatorVisitor::arm_SMMUL(Cond cond, Reg d, Reg m, bool R, Reg n) {
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// Multiply (Dual) instructions
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bool ArmTranslatorVisitor::arm_SMLAD(Cond cond, Reg d, Reg a, Reg m, bool M, Reg n) {
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return InterpretThisInstruction();
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if (a == Reg::PC)
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return arm_SMUAD(cond, d, m, M, n);
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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auto n32 = ir.GetRegister(n);
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auto m32 = ir.GetRegister(m);
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auto n_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(n32));
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auto m_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(m32));
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auto n_hi = ir.ArithmeticShiftRight(n32, ir.Imm8(16), ir.Imm1(0)).result;
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auto m_hi = ir.ArithmeticShiftRight(m32, ir.Imm8(16), ir.Imm1(0)).result;
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if (M)
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std::swap(m_lo, m_hi);
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auto product_lo = ir.Mul(n_lo, m_lo);
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auto product_hi = ir.Mul(n_hi, m_hi);
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auto addend = ir.GetRegister(a);
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auto result_overflow = ir.AddWithCarry(product_lo, product_hi, ir.Imm1(0));
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ir.OrQFlag(result_overflow.overflow);
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result_overflow = ir.AddWithCarry(result_overflow.result, addend, ir.Imm1(0));
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ir.SetRegister(d, result_overflow.result);
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ir.OrQFlag(result_overflow.overflow);
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}
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return true;
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}
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bool ArmTranslatorVisitor::arm_SMLALD(Cond cond, Reg dHi, Reg dLo, Reg m, bool M, Reg n) {
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return InterpretThisInstruction();
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if (dLo == Reg::PC || dHi == Reg::PC || n == Reg::PC || m == Reg::PC)
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return UnpredictableInstruction();
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if (dLo == dHi)
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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auto n32 = ir.GetRegister(n);
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auto m32 = ir.GetRegister(m);
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auto n_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(n32));
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auto m_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(m32));
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auto n_hi = ir.ArithmeticShiftRight(n32, ir.Imm8(16), ir.Imm1(0)).result;
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auto m_hi = ir.ArithmeticShiftRight(m32, ir.Imm8(16), ir.Imm1(0)).result;
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if (M)
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std::swap(m_lo, m_hi);
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auto product_lo = ir.SignExtendWordToLong(ir.Mul(n_lo, m_lo));
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auto product_hi = ir.SignExtendWordToLong(ir.Mul(n_hi, m_hi));
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auto addend = ir.Pack2x32To1x64(ir.GetRegister(dLo), ir.GetRegister(dHi));
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auto result = ir.Add64(ir.Add64(product_lo, product_hi), addend);
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ir.SetRegister(dLo, ir.LeastSignificantWord(result));
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ir.SetRegister(dHi, ir.MostSignificantWord(result).result);
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}
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return true;
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}
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bool ArmTranslatorVisitor::arm_SMLSD(Cond cond, Reg d, Reg a, Reg m, bool M, Reg n) {
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return InterpretThisInstruction();
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if (a == Reg::PC)
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return arm_SMUSD(cond, d, m, M, n);
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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auto n32 = ir.GetRegister(n);
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auto m32 = ir.GetRegister(m);
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auto n_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(n32));
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auto m_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(m32));
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auto n_hi = ir.ArithmeticShiftRight(n32, ir.Imm8(16), ir.Imm1(0)).result;
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auto m_hi = ir.ArithmeticShiftRight(m32, ir.Imm8(16), ir.Imm1(0)).result;
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if (M)
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std::swap(m_lo, m_hi);
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auto product_lo = ir.Mul(n_lo, m_lo);
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auto product_hi = ir.Mul(n_hi, m_hi);
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auto addend = ir.GetRegister(a);
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auto result_overflow = ir.AddWithCarry(ir.Sub(product_lo, product_hi), addend, ir.Imm1(0));
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ir.SetRegister(d, result_overflow.result);
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ir.OrQFlag(result_overflow.overflow);
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}
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return true;
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}
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bool ArmTranslatorVisitor::arm_SMLSLD(Cond cond, Reg dHi, Reg dLo, Reg m, bool M, Reg n) {
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return InterpretThisInstruction();
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if (dLo == Reg::PC || dHi == Reg::PC || n == Reg::PC || m == Reg::PC)
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return UnpredictableInstruction();
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if (dLo == dHi)
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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auto n32 = ir.GetRegister(n);
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auto m32 = ir.GetRegister(m);
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auto n_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(n32));
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auto m_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(m32));
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auto n_hi = ir.ArithmeticShiftRight(n32, ir.Imm8(16), ir.Imm1(0)).result;
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auto m_hi = ir.ArithmeticShiftRight(m32, ir.Imm8(16), ir.Imm1(0)).result;
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if (M)
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std::swap(m_lo, m_hi);
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auto product_lo = ir.SignExtendWordToLong(ir.Mul(n_lo, m_lo));
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auto product_hi = ir.SignExtendWordToLong(ir.Mul(n_hi, m_hi));
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auto addend = ir.Pack2x32To1x64(ir.GetRegister(dLo), ir.GetRegister(dHi));
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auto result = ir.Add64(ir.Sub64(product_lo, product_hi), addend);
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ir.SetRegister(dLo, ir.LeastSignificantWord(result));
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ir.SetRegister(dHi, ir.MostSignificantWord(result).result);
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}
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return true;
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}
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bool ArmTranslatorVisitor::arm_SMUAD(Cond cond, Reg d, Reg m, bool M, Reg n) {
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return InterpretThisInstruction();
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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auto n32 = ir.GetRegister(n);
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auto m32 = ir.GetRegister(m);
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auto n_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(n32));
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auto m_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(m32));
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auto n_hi = ir.ArithmeticShiftRight(n32, ir.Imm8(16), ir.Imm1(0)).result;
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auto m_hi = ir.ArithmeticShiftRight(m32, ir.Imm8(16), ir.Imm1(0)).result;
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if (M)
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std::swap(m_lo, m_hi);
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auto product_lo = ir.Mul(n_lo, m_lo);
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auto product_hi = ir.Mul(n_hi, m_hi);
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auto result_overflow = ir.AddWithCarry(product_lo, product_hi, ir.Imm1(0));
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ir.SetRegister(d, result_overflow.result);
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ir.OrQFlag(result_overflow.overflow);
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}
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return true;
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}
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bool ArmTranslatorVisitor::arm_SMUSD(Cond cond, Reg d, Reg m, bool M, Reg n) {
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return InterpretThisInstruction();
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
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return UnpredictableInstruction();
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if (ConditionPassed(cond)) {
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auto n32 = ir.GetRegister(n);
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auto m32 = ir.GetRegister(m);
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auto n_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(n32));
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auto m_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(m32));
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auto n_hi = ir.ArithmeticShiftRight(n32, ir.Imm8(16), ir.Imm1(0)).result;
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auto m_hi = ir.ArithmeticShiftRight(m32, ir.Imm8(16), ir.Imm1(0)).result;
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if (M)
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std::swap(m_lo, m_hi);
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auto product_lo = ir.Mul(n_lo, m_lo);
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auto product_hi = ir.Mul(n_hi, m_hi);
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auto result = ir.Sub(product_lo, product_hi);
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ir.SetRegister(d, result);
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}
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return true;
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}
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} // namespace Arm
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@ -792,7 +792,7 @@ TEST_CASE("Fuzz ARM multiply instructions", "[JitX64]") {
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Bits<12, 15>(inst) != Bits<16, 19>(inst);
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};
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const std::array<InstructionGenerator, 10> instructions = {{
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const std::array<InstructionGenerator, 21> instructions = {{
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InstructionGenerator("cccc0000001Sddddaaaammmm1001nnnn", validate_d_a_m_n), // MLA
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InstructionGenerator("cccc0000000Sdddd0000mmmm1001nnnn", validate_d_m_n), // MUL
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@ -802,27 +802,26 @@ TEST_CASE("Fuzz ARM multiply instructions", "[JitX64]") {
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InstructionGenerator("cccc0000101Sddddaaaammmm1001nnnn", validate_h_l_m_n), // UMLAL
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InstructionGenerator("cccc0000100Sddddaaaammmm1001nnnn", validate_h_l_m_n), // UMULL
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//InstructionGenerator("cccc00010100ddddaaaammmm1xy0nnnn", validate_d_a_m_n), // SMLALxy
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//InstructionGenerator("cccc00010000ddddaaaammmm1xy0nnnn", validate_d_a_m_n), // SMLAxy
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//InstructionGenerator("cccc00010110dddd0000mmmm1xy0nnnn", validate_d_m_n), // SMULxy
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InstructionGenerator("cccc00010100ddddaaaammmm1xy0nnnn", validate_h_l_m_n), // SMLALxy
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InstructionGenerator("cccc00010000ddddaaaammmm1xy0nnnn", validate_d_a_m_n), // SMLAxy
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InstructionGenerator("cccc00010110dddd0000mmmm1xy0nnnn", validate_d_m_n), // SMULxy
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//InstructionGenerator("cccc00010010ddddaaaammmm1y00nnnn", validate_d_a_m_n), // SMLAWy
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//InstructionGenerator("cccc00010010dddd0000mmmm1y10nnnn", validate_d_m_n), // SMULWy
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InstructionGenerator("cccc00010010ddddaaaammmm1y00nnnn", validate_d_a_m_n), // SMLAWy
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InstructionGenerator("cccc00010010dddd0000mmmm1y10nnnn", validate_d_m_n), // SMULWy
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InstructionGenerator("cccc01110101dddd1111mmmm00R1nnnn", validate_d_m_n), // SMMUL
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InstructionGenerator("cccc01110101ddddaaaammmm00R1nnnn", validate_d_a_m_n), // SMMLA
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InstructionGenerator("cccc01110101ddddaaaammmm11R1nnnn", validate_d_a_m_n), // SMMLS
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//InstructionGenerator("cccc01110000ddddaaaammmm00M1nnnn", validate_d_a_m_n), // SMLAD
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//InstructionGenerator("cccc01110100ddddaaaammmm00M1nnnn", validate_d_a_m_n), // SMLALD
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//InstructionGenerator("cccc01110000ddddaaaammmm01M1nnnn", validate_d_a_m_n), // SMLSD
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//InstructionGenerator("cccc01110100ddddaaaammmm01M1nnnn", validate_d_a_m_n), // SMLSLD
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//InstructionGenerator("cccc01110000dddd1111mmmm00M1nnnn", validate_d_m_n), // SMUAD
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//InstructionGenerator("cccc01110000dddd1111mmmm01M1nnnn", validate_d_m_n), // SMUSD
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InstructionGenerator("cccc01110000ddddaaaammmm00M1nnnn", validate_d_a_m_n), // SMLAD
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InstructionGenerator("cccc01110100ddddaaaammmm00M1nnnn", validate_h_l_m_n), // SMLALD
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InstructionGenerator("cccc01110000ddddaaaammmm01M1nnnn", validate_d_a_m_n), // SMLSD
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InstructionGenerator("cccc01110100ddddaaaammmm01M1nnnn", validate_h_l_m_n), // SMLSLD
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InstructionGenerator("cccc01110000dddd1111mmmm00M1nnnn", validate_d_m_n), // SMUAD
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InstructionGenerator("cccc01110000dddd1111mmmm01M1nnnn", validate_d_m_n), // SMUSD
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}};
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SECTION("Multiply") {
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FuzzJitArm(2, 2, 10000, [&]() -> u32 {
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FuzzJitArm(1, 1, 10000, [&]() -> u32 {
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return instructions[RandInt<size_t>(0, instructions.size() - 1)].Generate();
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});
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}
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@ -852,6 +851,30 @@ TEST_CASE("Fuzz ARM parallel instructions", "[JitX64]") {
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}
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}
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TEST_CASE( "SMUAD", "[JitX64]" ) {
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Dynarmic::Jit jit{GetUserCallbacks()};
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code_mem.fill({});
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code_mem[0] = 0xE700F211; // smuad r0, r1, r2
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jit.Regs() = {
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0, // Rd
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0x80008000, // Rn
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0x80008000, // Rm
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0,
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0, 0, 0, 0,
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0, 0, 0, 0,
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0, 0, 0, 0,
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};
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jit.Cpsr() = 0x000001d0; // User-mode
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jit.Run(6);
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REQUIRE(jit.Regs()[0] == 0x80000000);
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REQUIRE(jit.Regs()[1] == 0x80008000);
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REQUIRE(jit.Regs()[2] == 0x80008000);
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REQUIRE(jit.Cpsr() == 0x080001d0);
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}
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TEST_CASE("VFP: VPUSH, VPOP", "[JitX64][vfp]") {
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const auto is_valid = [](u32 instr) -> bool {
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auto regs = (instr & 0x100) ? (Bits<0, 7>(instr) >> 1) : Bits<0, 7>(instr);
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