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emit_arm64_a32: A32SetCpsrNZC: Handle immediate

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Merry 2022-07-31 08:49:02 +01:00 committed by merry
parent 65a7d9be8d
commit db5db43fd4
1 changed files with 39 additions and 18 deletions
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21
src/dynarmic/backend/arm64/emit_arm64_a32.cpp
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@ -323,6 +323,26 @@ void EmitIR<IR::Opcode::A32SetCpsrNZC>(oaknut::CodeGenerator& code, EmitContext&
// TODO: Track latent value
if (args[0].IsImmediate()) {
if (args[1].IsImmediate()) {
const u32 carry = args[1].GetImmediateU1() ? 0x2000'0000 : 0;
code.LDR(Wscratch0, Xstate, offsetof(A32JitState, cpsr_nzcv));
code.AND(Wscratch0, Wscratch0, 0x10000000);
if (carry) {
code.ORR(Wscratch0, Wscratch0, carry);
}
code.STR(Wscratch0, Xstate, offsetof(A32JitState, cpsr_nzcv));
} else {
auto Wc = ctx.reg_alloc.ReadW(args[1]);
RegAlloc::Realize(Wc);
code.LDR(Wscratch0, Xstate, offsetof(A32JitState, cpsr_nzcv));
code.AND(Wscratch0, Wscratch0, 0x10000000);
code.ORR(Wscratch0, Wscratch0, Wc);
code.STR(Wscratch0, Xstate, offsetof(A32JitState, cpsr_nzcv));
}
} else {
if (args[1].IsImmediate()) {
const u32 carry = args[1].GetImmediateU1() ? 0x2000'0000 : 0;
auto Wnz = ctx.reg_alloc.ReadW(args[0]);
@ -347,6 +367,7 @@ void EmitIR<IR::Opcode::A32SetCpsrNZC>(oaknut::CodeGenerator& code, EmitContext&
code.STR(Wscratch0, Xstate, offsetof(A32JitState, cpsr_nzcv));
}
}
}
template<>
void EmitIR<IR::Opcode::A32GetCFlag>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {