A32: Implement ASIMD VQRDMULH
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3 changed files with 25 additions and 1 deletions
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@ -33,7 +33,7 @@ INST(asimd_VMUL, "VMUL", "1111001P0Dzznnnndddd100
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INST(asimd_VMULL, "VMULL", "1111001U1Dzznnnndddd11P0N0M0mmmm") // ASIMD
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//INST(asimd_VPMAX, "VPMAX/VPMIN", "1111001U0-CC--------1010---B----") // ASIMD
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INST(asimd_VQDMULH, "VQDMULH", "111100100Dzznnnndddd1011NQM0mmmm") // ASIMD
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//INST(asimd_VQRDMULH, "VQRDMULH", "111100110-CC--------1011---0----") // ASIMD
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INST(asimd_VQRDMULH, "VQRDMULH", "111100110Dzznnnndddd1011NQM0mmmm") // ASIMD
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INST(asimd_VPADD, "VPADD", "111100100Dzznnnndddd1011NQM1mmmm") // ASIMD
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INST(asimd_VFMA, "VFMA", "111100100D0znnnndddd1100NQM1mmmm") // ASIMD
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INST(asimd_VFMS, "VFMS", "111100100D1znnnndddd1100NQM1mmmm") // ASIMD
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@ -645,6 +645,29 @@ bool ArmTranslatorVisitor::asimd_VQDMULH(bool D, size_t sz, size_t Vn, size_t Vd
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return true;
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}
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bool ArmTranslatorVisitor::asimd_VQRDMULH(bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
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if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) {
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return UndefinedInstruction();
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}
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if (sz == 0b00 || sz == 0b11) {
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return UndefinedInstruction();
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}
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const size_t esize = 8U << sz;
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const auto d = ToVector(Q, Vd, D);
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const auto m = ToVector(Q, Vm, M);
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const auto n = ToVector(Q, Vn, N);
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const auto reg_n = ir.GetVector(n);
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const auto reg_m = ir.GetVector(m);
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const auto multiply = ir.VectorSignedSaturatedDoublingMultiply(esize, reg_n, reg_m);
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const auto result = ir.VectorAdd(esize, multiply.upper, ir.VectorLogicalShiftRight(esize, multiply.lower, static_cast<u8>(esize - 1)));
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ir.SetVector(d, result);
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return true;
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}
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bool ArmTranslatorVisitor::asimd_VMULL(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool P, bool N, bool M, size_t Vm) {
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if (sz == 0b11 || (P & (U || sz == 0b10)) || Common::Bit<0>(Vd)) {
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return UndefinedInstruction();
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@ -481,6 +481,7 @@ struct ArmTranslatorVisitor final {
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bool asimd_VMUL(bool P, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
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bool asimd_VMULL(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool P, bool N, bool M, size_t Vm);
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bool asimd_VQDMULH(bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
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bool asimd_VQRDMULH(bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
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bool asimd_VPADD(bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
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bool asimd_VFMA(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
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bool asimd_VFMS(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
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