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A64: Implement half-precision scalar variant of FRECPS

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Lioncash 2019-04-13 19:03:58 -04:00 committed by MerryMage
parent 825a3ea16f
commit de43f011a7
2 changed files with 12 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -384,7 +384,7 @@ INST(DUP_elt_1, "DUP (element)", "01011
INST(FMULX_vec_2, "FMULX", "010111100z1mmmmm110111nnnnnddddd")
//INST(FCMEQ_reg_1, "FCMEQ (register)", "01011110010mmmmm001001nnnnnddddd")
INST(FCMEQ_reg_2, "FCMEQ (register)", "010111100z1mmmmm111001nnnnnddddd")
//INST(FRECPS_1, "FRECPS", "01011110010mmmmm001111nnnnnddddd")
INST(FRECPS_1, "FRECPS", "01011110010mmmmm001111nnnnnddddd")
INST(FRECPS_2, "FRECPS", "010111100z1mmmmm111111nnnnnddddd")
//INST(FRSQRTS_1, "FRSQRTS", "01011110110mmmmm001111nnnnnddddd")
INST(FRSQRTS_2, "FRSQRTS", "010111101z1mmmmm111111nnnnnddddd")

11
src/frontend/A64/translate/impl/simd_scalar_three_same.cpp
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@ -294,6 +294,17 @@ bool TranslatorVisitor::FMULX_vec_2(bool sz, Vec Vm, Vec Vn, Vec Vd) {
return true;
}
bool TranslatorVisitor::FRECPS_1(Vec Vm, Vec Vn, Vec Vd) {
const size_t esize = 16;
const IR::U16 operand1 = V_scalar(esize, Vn);
const IR::U16 operand2 = V_scalar(esize, Vm);
const IR::U16 result = ir.FPRecipStepFused(operand1, operand2);
V_scalar(esize, Vd, result);
return true;
}
bool TranslatorVisitor::FRECPS_2(bool sz, Vec Vm, Vec Vn, Vec Vd) {
const size_t esize = sz ? 64 : 32;