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A32: Implement ASIMD VQRSHRN

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This commit is contained in:
MerryMage 2020-06-21 17:40:03 +01:00
parent 589d717af5
commit df58a429ee
3 changed files with 7 additions and 1 deletions
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2
src/frontend/A32/decoder/asimd.inc
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@ -76,7 +76,7 @@ INST(asimd_VSHRN, "VSHRN", "111100101Diiiiiidddd100
//INST(asimd_VQSHRUN, "VQSHRUN", "111100111-vvv-------100000-1----") // ASIMD //INST(asimd_VQSHRUN, "VQSHRUN", "111100111-vvv-------100000-1----") // ASIMD
INST(asimd_VQRSHRUN, "VQRSHRUN", "111100111Diiiiiidddd100001M1mmmm") // ASIMD INST(asimd_VQRSHRUN, "VQRSHRUN", "111100111Diiiiiidddd100001M1mmmm") // ASIMD
//INST(asimd_VQSHRN, "VQSHRN", "1111001U1-vvv-------100100-1----") // ASIMD //INST(asimd_VQSHRN, "VQSHRN", "1111001U1-vvv-------100100-1----") // ASIMD
//INST(asimd_VQRSHRN, "VQRSHRN", "1111001U1-vvv-------100101-1----") // ASIMD INST(asimd_VQRSHRN, "VQRSHRN", "1111001U1Diiiiiidddd100101M1mmmm") // ASIMD
//INST(asimd_SHLL, "SHLL", "1111001U1-vvv-------101000-1----") // ASIMD //INST(asimd_SHLL, "SHLL", "1111001U1-vvv-------101000-1----") // ASIMD
//INST(asimd_VCVT_fixed, "VCVT (fixed-point)", "1111001U1-vvv-------111x0B-1----") // ASIMD //INST(asimd_VCVT_fixed, "VCVT (fixed-point)", "1111001U1-vvv-------111x0B-1----") // ASIMD

5
src/frontend/A32/translate/impl/asimd_two_regs_shift.cpp
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@ -247,4 +247,9 @@ bool ArmTranslatorVisitor::asimd_VQRSHRUN(bool D, size_t imm6, size_t Vd, bool M
Rounding::Round, Narrowing::SaturateToUnsigned, Signedness::Signed); Rounding::Round, Narrowing::SaturateToUnsigned, Signedness::Signed);
} }
bool ArmTranslatorVisitor::asimd_VQRSHRN(bool U, bool D, size_t imm6, size_t Vd, bool M, size_t Vm) {
return ShiftRightNarrowing(*this, D, imm6, Vd, M, Vm,
Rounding::Round, U ? Narrowing::SaturateToUnsigned : Narrowing::SaturateToSigned, U ? Signedness::Unsigned : Signedness::Signed);
}
} // namespace Dynarmic::A32 } // namespace Dynarmic::A32

1
src/frontend/A32/translate/impl/translate_arm.h
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@ -510,6 +510,7 @@ struct ArmTranslatorVisitor final {
bool asimd_VSLI(bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm); bool asimd_VSLI(bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm);
bool asimd_VSHRN(bool D, size_t imm6, size_t Vd, bool M, size_t Vm); bool asimd_VSHRN(bool D, size_t imm6, size_t Vd, bool M, size_t Vm);
bool asimd_VQRSHRUN(bool D, size_t imm6, size_t Vd, bool M, size_t Vm); bool asimd_VQRSHRUN(bool D, size_t imm6, size_t Vd, bool M, size_t Vm);
bool asimd_VQRSHRN(bool U, bool D, size_t imm6, size_t Vd, bool M, size_t Vm);
// Advanced SIMD two register, miscellaneous // Advanced SIMD two register, miscellaneous
bool asimd_VREV(bool D, size_t sz, size_t Vd, size_t op, bool Q, bool M, size_t Vm); bool asimd_VREV(bool D, size_t sz, size_t Vd, size_t op, bool Q, bool M, size_t Vm);