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A32: Implement ASIMD VSUB (floating-point)

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This commit is contained in:
MerryMage 2020-06-20 13:39:03 +01:00
parent 4c939b9d0a
commit e006f0a205
7 changed files with 16 additions and 9 deletions
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4
src/backend/x64/emit_x64_vector_floating_point.cpp
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@ -1401,11 +1401,11 @@ void EmitX64::EmitFPVectorSqrt64(EmitContext& ctx, IR::Inst* inst) {
} }
void EmitX64::EmitFPVectorSub32(EmitContext& ctx, IR::Inst* inst) { void EmitX64::EmitFPVectorSub32(EmitContext& ctx, IR::Inst* inst) {
EmitThreeOpVectorOperation<32, DefaultIndexer>(code, ctx, inst, &Xbyak::CodeGenerator::subps); EmitThreeOpVectorOperation<32, DefaultIndexer, FpcrControlledArgument::Present>(code, ctx, inst, &Xbyak::CodeGenerator::subps);
} }
void EmitX64::EmitFPVectorSub64(EmitContext& ctx, IR::Inst* inst) { void EmitX64::EmitFPVectorSub64(EmitContext& ctx, IR::Inst* inst) {
EmitThreeOpVectorOperation<64, DefaultIndexer>(code, ctx, inst, &Xbyak::CodeGenerator::subpd); EmitThreeOpVectorOperation<64, DefaultIndexer, FpcrControlledArgument::Present>(code, ctx, inst, &Xbyak::CodeGenerator::subpd);
} }
template<size_t fsize, bool unsigned_> template<size_t fsize, bool unsigned_>

2
src/frontend/A32/decoder/asimd.inc
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@ -34,7 +34,7 @@ INST(asimd_VMUL, "VMUL", "1111001P0Dzznnnndddd100
//INST(asimd_VPADD, "VPADD", "1111001U0-CC--------1011---1----") // ASIMD //INST(asimd_VPADD, "VPADD", "1111001U0-CC--------1011---1----") // ASIMD
//INST(asimd_VFMA, "VFMA/VFMS", "111100100-CC--------1100---1----") // ASIMD //INST(asimd_VFMA, "VFMA/VFMS", "111100100-CC--------1100---1----") // ASIMD
INST(asimd_VADD_float, "VADD (floating-point)", "111100100D0znnnndddd1101NQM0mmmm") // ASIMD INST(asimd_VADD_float, "VADD (floating-point)", "111100100D0znnnndddd1101NQM0mmmm") // ASIMD
//INST(asimd_VSUB_float, "VSUB (floating-point)", "111100100-1C--------1101---0----") // ASIMD INST(asimd_VSUB_float, "VSUB (floating-point)", "111100100D1znnnndddd1101NQM0mmmm") // ASIMD
//INST(asimd_VPADD_float, "VPADD (floating-point)", "111100110-0C--------1101---0----") // ASIMD //INST(asimd_VPADD_float, "VPADD (floating-point)", "111100110-0C--------1101---0----") // ASIMD
//INST(asimd_VABD_float, "VABD (floating-point)", "111100110-1C--------1101---0----") // ASIMD //INST(asimd_VABD_float, "VABD (floating-point)", "111100110-1C--------1101---0----") // ASIMD
//INST(asimd_VMLA_float, "VMLA (floating-point)", "111100100-CC--------1101---1----") // ASIMD //INST(asimd_VMLA_float, "VMLA (floating-point)", "111100100-CC--------1101---1----") // ASIMD

6
src/frontend/A32/translate/impl/asimd_three_same.cpp
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@ -362,6 +362,12 @@ bool ArmTranslatorVisitor::asimd_VADD_float(bool D, bool sz, size_t Vn, size_t V
}); });
} }
bool ArmTranslatorVisitor::asimd_VSUB_float(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
return FloatingPointInstruction(*this, D, sz, Vn, Vd, N, Q, M, Vm, [this](const auto&, const auto& reg_n, const auto& reg_m) {
return ir.FPVectorSub(32, reg_n, reg_m, false);
});
}
bool ArmTranslatorVisitor::asimd_VMUL_float(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) { bool ArmTranslatorVisitor::asimd_VMUL_float(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
return FloatingPointInstruction(*this, D, sz, Vn, Vd, N, Q, M, Vm, [this](const auto&, const auto& reg_n, const auto& reg_m) { return FloatingPointInstruction(*this, D, sz, Vn, Vd, N, Q, M, Vm, [this](const auto&, const auto& reg_n, const auto& reg_m) {
return ir.FPVectorMul(32, reg_n, reg_m, false); return ir.FPVectorMul(32, reg_n, reg_m, false);

1
src/frontend/A32/translate/impl/translate_arm.h
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@ -463,6 +463,7 @@ struct ArmTranslatorVisitor final {
bool asimd_VTST(bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm); bool asimd_VTST(bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
bool asimd_VMUL(bool P, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm); bool asimd_VMUL(bool P, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
bool asimd_VADD_float(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm); bool asimd_VADD_float(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
bool asimd_VSUB_float(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
bool asimd_VMUL_float(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm); bool asimd_VMUL_float(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
bool asimd_VMAX_float(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm); bool asimd_VMAX_float(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
bool asimd_VMIN_float(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm); bool asimd_VMIN_float(bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);

6
src/frontend/ir/ir_emitter.cpp
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@ -2513,12 +2513,12 @@ U128 IREmitter::FPVectorSqrt(size_t esize, const U128& a) {
UNREACHABLE(); UNREACHABLE();
} }
U128 IREmitter::FPVectorSub(size_t esize, const U128& a, const U128& b) { U128 IREmitter::FPVectorSub(size_t esize, const U128& a, const U128& b, bool fpcr_controlled) {
switch (esize) { switch (esize) {
case 32: case 32:
return Inst<U128>(Opcode::FPVectorSub32, a, b); return Inst<U128>(Opcode::FPVectorSub32, a, b, Imm1(fpcr_controlled));
case 64: case 64:
return Inst<U128>(Opcode::FPVectorSub64, a, b); return Inst<U128>(Opcode::FPVectorSub64, a, b, Imm1(fpcr_controlled));
} }
UNREACHABLE(); UNREACHABLE();
} }

2
src/frontend/ir/ir_emitter.h
View file

@ -366,7 +366,7 @@ public:
U128 FPVectorRSqrtEstimate(size_t esize, const U128& a); U128 FPVectorRSqrtEstimate(size_t esize, const U128& a);
U128 FPVectorRSqrtStepFused(size_t esize, const U128& a, const U128& b); U128 FPVectorRSqrtStepFused(size_t esize, const U128& a, const U128& b);
U128 FPVectorSqrt(size_t esize, const U128& a); U128 FPVectorSqrt(size_t esize, const U128& a);
U128 FPVectorSub(size_t esize, const U128& a, const U128& b); U128 FPVectorSub(size_t esize, const U128& a, const U128& b, bool fpcr_controlled = true);
U128 FPVectorToSignedFixed(size_t esize, const U128& a, size_t fbits, FP::RoundingMode rounding); U128 FPVectorToSignedFixed(size_t esize, const U128& a, size_t fbits, FP::RoundingMode rounding);
U128 FPVectorToUnsignedFixed(size_t esize, const U128& a, size_t fbits, FP::RoundingMode rounding); U128 FPVectorToUnsignedFixed(size_t esize, const U128& a, size_t fbits, FP::RoundingMode rounding);

4
src/frontend/ir/opcodes.inc
View file

@ -630,8 +630,8 @@ OPCODE(FPVectorRSqrtStepFused32, U128, U128
OPCODE(FPVectorRSqrtStepFused64, U128, U128, U128 ) OPCODE(FPVectorRSqrtStepFused64, U128, U128, U128 )
OPCODE(FPVectorSqrt32, U128, U128 ) OPCODE(FPVectorSqrt32, U128, U128 )
OPCODE(FPVectorSqrt64, U128, U128 ) OPCODE(FPVectorSqrt64, U128, U128 )
OPCODE(FPVectorSub32, U128, U128, U128 ) OPCODE(FPVectorSub32, U128, U128, U128, U1 )
OPCODE(FPVectorSub64, U128, U128, U128 ) OPCODE(FPVectorSub64, U128, U128, U128, U1 )
OPCODE(FPVectorToSignedFixed16, U128, U128, U8, U8 ) OPCODE(FPVectorToSignedFixed16, U128, U128, U8, U8 )
OPCODE(FPVectorToSignedFixed32, U128, U128, U8, U8 ) OPCODE(FPVectorToSignedFixed32, U128, U128, U8, U8 )
OPCODE(FPVectorToSignedFixed64, U128, U128, U8, U8 ) OPCODE(FPVectorToSignedFixed64, U128, U128, U8, U8 )