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A64: Implement FABD in terms of existing IR instructions

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Fixes NaN issue. Closes #306.
This commit is contained in:
MerryMage 2018-07-16 16:51:16 +01:00
parent 1dbe9d95e6
commit e18fca17dc
6 changed files with 5 additions and 42 deletions
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22
src/backend_x64/emit_x64_vector_floating_point.cpp
View file

@ -224,28 +224,6 @@ static void EmitVectorOperation64(BlockOfCode& code, EmitContext& ctx, IR::Inst*
ctx.reg_alloc.DefineValue(inst, result);
}
void EmitX64::EmitFPVectorAbsoluteDifference32(EmitContext& ctx, IR::Inst* inst) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
const Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(args[0]);
const Xbyak::Xmm b = ctx.reg_alloc.UseXmm(args[1]);
code.subps(a, b);
code.andps(a, code.MConst(xword, 0x7FFFFFFF7FFFFFFF, 0x7FFFFFFF7FFFFFFF));
ctx.reg_alloc.DefineValue(inst, a);
}
void EmitX64::EmitFPVectorAbsoluteDifference64(EmitContext& ctx, IR::Inst* inst) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
const Xbyak::Xmm a = ctx.reg_alloc.UseScratchXmm(args[0]);
const Xbyak::Xmm b = ctx.reg_alloc.UseXmm(args[1]);
code.subpd(a, b);
code.andpd(a, code.MConst(xword, 0x7FFFFFFFFFFFFFFF, 0x7FFFFFFFFFFFFFFF));
ctx.reg_alloc.DefineValue(inst, a);
}
void EmitX64::EmitFPVectorAbs16(EmitContext& ctx, IR::Inst* inst) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst);

9
src/frontend/A64/translate/impl/simd_scalar_three_same.cpp
View file

@ -173,12 +173,11 @@ bool TranslatorVisitor::CMTST_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
bool TranslatorVisitor::FABD_2(bool sz, Vec Vm, Vec Vn, Vec Vd) {
const size_t esize = sz ? 64 : 32;
const IR::U128 operand1 = V(esize, Vn);
const IR::U128 operand2 = V(esize, Vm);
const IR::U128 difference = ir.FPVectorAbsoluteDifference(esize, operand1, operand2);
const IR::U128 result = ir.VectorZeroUpper(difference);
const IR::U32U64 operand1 = V_scalar(esize, Vn);
const IR::U32U64 operand2 = V_scalar(esize, Vm);
const IR::U32U64 result = ir.FPAbs(ir.FPSub(operand1, operand2, true));
V(128, Vd, result);
V_scalar(esize, Vd, result);
return true;
}

2
src/frontend/A64/translate/impl/simd_three_same.cpp
View file

@ -384,7 +384,7 @@ bool TranslatorVisitor::FABD_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
const IR::U128 operand1 = V(datasize, Vn);
const IR::U128 operand2 = V(datasize, Vm);
const IR::U128 result = ir.FPVectorAbsoluteDifference(esize, operand1, operand2);
const IR::U128 result = ir.FPVectorAbs(esize, ir.FPVectorSub(esize, operand1, operand2));
V(datasize, Vd, result);
return true;

11
src/frontend/ir/ir_emitter.cpp
View file

@ -1577,17 +1577,6 @@ U128 IREmitter::FPVectorAbs(size_t esize, const U128& a) {
return {};
}
U128 IREmitter::FPVectorAbsoluteDifference(size_t esize, const U128& a, const U128& b) {
switch (esize) {
case 32:
return Inst<U128>(Opcode::FPVectorAbsoluteDifference32, a, b);
case 64:
return Inst<U128>(Opcode::FPVectorAbsoluteDifference64, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::FPVectorAdd(size_t esize, const U128& a, const U128& b) {
switch (esize) {
case 32:

1
src/frontend/ir/ir_emitter.h
View file

@ -289,7 +289,6 @@ public:
U32 FPU64ToSingle(const U64& a, bool round_to_nearest, bool fpscr_controlled);
U128 FPVectorAbs(size_t esize, const U128& a);
U128 FPVectorAbsoluteDifference(size_t esize, const U128& a, const U128& b);
U128 FPVectorAdd(size_t esize, const U128& a, const U128& b);
U128 FPVectorDiv(size_t esize, const U128& a, const U128& b);
U128 FPVectorEqual(size_t esize, const U128& a, const U128& b);

2
src/frontend/ir/opcodes.inc
View file

@ -415,8 +415,6 @@ OPCODE(FPS64ToSingle, T::U32, T::U64, T::U
OPCODE(FPVectorAbs16, T::U128, T::U128 )
OPCODE(FPVectorAbs32, T::U128, T::U128 )
OPCODE(FPVectorAbs64, T::U128, T::U128 )
OPCODE(FPVectorAbsoluteDifference32, T::U128, T::U128, T::U128 )
OPCODE(FPVectorAbsoluteDifference64, T::U128, T::U128, T::U128 )
OPCODE(FPVectorAdd32, T::U128, T::U128, T::U128 )
OPCODE(FPVectorAdd64, T::U128, T::U128, T::U128 )
OPCODE(FPVectorDiv32, T::U128, T::U128, T::U128 )