A64: Implement SADDLV
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2 changed files with 49 additions and 30 deletions
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@ -659,7 +659,7 @@ INST(FCMLE_4, "FCMLE (zero)", "0Q101
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//INST(FSQRT_2, "FSQRT (vector)", "0Q1011101z100001111110nnnnnddddd")
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//INST(FSQRT_2, "FSQRT (vector)", "0Q1011101z100001111110nnnnnddddd")
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// Data Processing - FP and SIMD - SIMD across lanes
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// Data Processing - FP and SIMD - SIMD across lanes
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//INST(SADDLV, "SADDLV", "0Q001110zz110000001110nnnnnddddd")
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INST(SADDLV, "SADDLV", "0Q001110zz110000001110nnnnnddddd")
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//INST(SMAXV, "SMAXV", "0Q001110zz110000101010nnnnnddddd")
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//INST(SMAXV, "SMAXV", "0Q001110zz110000101010nnnnnddddd")
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//INST(SMINV, "SMINV", "0Q001110zz110001101010nnnnnddddd")
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//INST(SMINV, "SMINV", "0Q001110zz110001101010nnnnnddddd")
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INST(ADDV, "ADDV", "0Q001110zz110001101110nnnnnddddd")
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INST(ADDV, "ADDV", "0Q001110zz110001101110nnnnnddddd")
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@ -7,6 +7,49 @@
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#include "frontend/A64/translate/impl/impl.h"
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#include "frontend/A64/translate/impl/impl.h"
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namespace Dynarmic::A64 {
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namespace Dynarmic::A64 {
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namespace {
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enum class Signedness {
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Signed,
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Unsigned
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};
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bool LongAdd(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vn, Vec Vd, Signedness sign) {
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if ((size == 0b10 && !Q) || size == 0b11) {
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return v.ReservedValue();
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}
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const size_t esize = 8 << size.ZeroExtend();
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const size_t datasize = Q ? 128 : 64;
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const size_t elements = datasize / esize;
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const IR::U128 operand = v.V(datasize, Vn);
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const auto get_element = [&](IR::U128 vec, size_t element) {
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const auto vec_element = v.ir.VectorGetElement(esize, vec, element);
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if (sign == Signedness::Signed) {
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return v.ir.SignExtendToLong(vec_element);
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}
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return v.ir.ZeroExtendToLong(vec_element);
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};
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IR::U64 sum = get_element(operand, 0);
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for (size_t i = 1; i < elements; i++) {
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sum = v.ir.Add(sum, get_element(operand, i));
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}
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if (size == 0b00) {
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v.V(datasize, Vd, v.ir.ZeroExtendToQuad(v.ir.LeastSignificantHalf(sum)));
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} else if (size == 0b01) {
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v.V(datasize, Vd, v.ir.ZeroExtendToQuad(v.ir.LeastSignificantWord(sum)));
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} else {
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v.V(datasize, Vd, v.ir.ZeroExtendToQuad(sum));
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}
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return true;
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}
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} // Anonymous namespace
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bool TranslatorVisitor::ADDV(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
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bool TranslatorVisitor::ADDV(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
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if ((size == 0b10 && !Q) || size == 0b11) {
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if ((size == 0b10 && !Q) || size == 0b11) {
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@ -39,35 +82,11 @@ bool TranslatorVisitor::ADDV(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
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return true;
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return true;
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}
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}
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bool TranslatorVisitor::SADDLV(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
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return LongAdd(*this, Q, size, Vn, Vd, Signedness::Signed);
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}
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bool TranslatorVisitor::UADDLV(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
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bool TranslatorVisitor::UADDLV(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
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if ((size == 0b10 && !Q) || size == 0b11) {
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return LongAdd(*this, Q, size, Vn, Vd, Signedness::Unsigned);
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return ReservedValue();
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}
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}
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const size_t esize = 8 << size.ZeroExtend();
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const size_t datasize = Q ? 128 : 64;
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const size_t elements = datasize / esize;
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const IR::U128 operand = V(datasize, Vn);
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const auto get_element = [&](IR::U128 vec, size_t element) {
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return ir.ZeroExtendToLong(ir.VectorGetElement(esize, vec, element));
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};
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IR::U64 sum = get_element(operand, 0);
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for (size_t i = 1; i < elements; i++) {
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sum = ir.Add(sum, get_element(operand, i));
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}
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if (size == 0b00) {
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V(datasize, Vd, ir.ZeroExtendToQuad(ir.LeastSignificantHalf(sum)));
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} else if (size == 0b01) {
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V(datasize, Vd, ir.ZeroExtendToQuad(ir.LeastSignificantWord(sum)));
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} else {
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V(datasize, Vd, ir.ZeroExtendToQuad(sum));
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}
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return true;
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}
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} // namespace Dynarmic::A64
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} // namespace Dynarmic::A64
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